Adv Antest Corporation

Shigeki Takizawa

Satoshi Iwamoto

Koichi Yatsuka

Toshio Matsuura

Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section.

Test equipment

A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

Test apparatus and calibration method

There is provided an interconnection substrate used in skew adjustment between output pins in a test apparatus, the test apparatus supplying a test signal to a device under test to test the device under test, the interconnection substrate including: a first terminal coupled to a first output pin that outputs the test signal; a second terminal coupled to a second output pin that outputs the test signal; a first interconnection connecting the first terminal to a bonding node; a second interconnection connecting the second terminal to the bonding node; and a third interconnection connecting the bonding node to an output node, where the first interconnection and the second interconnection have a length equal to each other.

Interconnection substrate, skew measurement method, and test apparatus

A test apparatus includes a test module including a correcting unit for correcting the timing at which the test signal is to be supplied to the device under test or a voltage level of the test signal to the device under test, a correction value holding unit for holding a correction value used for a correction by the correcting unit, and an identification information storing unit for storing test module identification information, which is identification information of the test module, a correction value database for storing the correction value to be held by the correction value holding unit of the test module identified by the test module identification information, in order that the correction value corresponds to the test module identification information, and control means for retrieving the correction value stored by the correction value database, wherein the correction value corresponds to the test module identification information stored by the identification information storing unit, and controlling the correction value holding unit to hold the correction value.

Test apparatus, correction value managing method, and computer program

A semiconductor test system having a high repetition rate and small jitter clock generator for supplying the clock signal to a device under test (DUT). The semiconductor test system includes a clock generator for generating a reference clock signal, a frame processor for producing a clock signal of predetermined waveform based on the reference clock signal from the clock generator, a phase lock loop (PLL) circuit for generating a clock signal based on the clock signal from the frame processor where the frequency generated by the PLL circuit is higher than that of the clock signal from the frame processor, and a driver for directly receiving the clock signal from the PLL circuit to apply the clock signal to the DUT with a predetermined amplitude.

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Tokyo, Japan

Shigeki Takizawa