Nec Electronics Corporation

Shigeki Sakai

Masaharu Mizuno

Naotaka Maeda

The master slice type semiconductor integrated circuit includes sequential circuit cells ( ) and combinational circuit cells ( ), which are alternately arranged in an inner core area on a semiconductor chip ( ), and a plurality of selective driving elements (MC to MC , MC to MC and MC to MC ), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing the inner core area. The plurality of selective driving elements are placed and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal. Due to this configuration, it is possible to cope with a poliphase clock, and also possible to reduce a clock skew between circuits, and further possible to provide a master slice type semiconductor integrated circuit in which an electric power consumption can be reduced.

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Tokyo, Japan

Shigeki Sakai