Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (Corporation)

Globalfoundries Inc.

Shiang Yang Ong

Namchil Mun

Jan Hoentschel

Stefan Flachowsky

Elgin Kiok Quek

Jae Gon Lee

Chung Foong Tan

Thilo Scheiper

Jeoung Mo Koo

Raj Verma Purakh

Eng Huat Toh

Purakh Raj Verma

Jinping Liu

Huang Liu

Liang Choo Hsia

Lee Wee Teo

James Yong Meng Lee

Chung Woh Lai

Ran Yan

Zhao Lun

Johnny Widodo

Dong Kyun Sohn

Shailendra Mishra

Fang Chen

Bangun Indajang

Eng Fong Chor

Wen Zhi Gao

Yew Tuck Chow

Vincent Leong

Hyeok Jae Lee

Hung Chang Liao

Zhongxiu Yang

Jianbo Zhou

Shesh Mani Pandey

Francis Lionel Benistant

Ming Li

Nicolas Sassiat

Ke Dong

Kun Liu

Torben Balzer

Tat Wei Chua

Mun Tat Yap

Sivakami Subramanian

A trench isolation structure and method of making the same is provided. The trench isolation structure comprises a trench in a substrate, the trench having a bottom surface and sidewalls. A polycrystalline material is at least partially in the trench and an amorphous layer is over the polycrystalline material.

Trench isolation structures and methods of making thereof

Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

Deep trench isolation structures with a substrate connection

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer

The present invention discloses a Schottky diode. The Schottky diode comprises a substrate having a device well. A drift region is disposed within the device well. A guard ring region is disposed within the device well and adjacent to the drift region. A field isolation region and a dielectric film are disposed on a top substrate surface. The dielectric film is aligned to the field isolation region. A field plate is disposed over the field isolation region and the dielectric film. The field plate completely covers a top surface of the dielectric film and partially overlaps the guard ring region. A conductive contact layer is disposed adjacent to the dielectric film. The conductive contact layer contacts a portion of the device well to define a Schottky diode interface.

High voltage Schottky diode and manufacturing method thereof

A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.

Low on resistance high voltage metal oxide semiconductor transistor

The present disclosure relates to semiconductor structures and, more particularly, to contact structures to deep trench isolation structures and methods of manufacture. The structure includes: a deep trench structure lined with insulator material on sidewalls thereof; conductive material filling the deep trench structure; a local oxide extending above the trench on exposed portions of the insulator material; an interlevel dielectric material on the local oxide and the conductive material filling the deep trench structure; and a contact in the interlevel dielectric material, extending to the conductive material and on a side of the local oxide.

Contact structures to deep trench isolation structures and method of nanufacturing the same

Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes determining a guard ring width within an integrated circuit design layout, where a guard ring with the guard ring width surrounds an active area in the integrated circuit design layout. A deep trench location is calculated for replacing the guard ring, where the deep trench location depends on the guard ring width. The guard ring in the integrated circuit design layout is replaced with a deep trench having the deep trench location. The deep trench is formed within a substrate at the deep trench location, where the deep trench surrounds the active area.

Integrated circuits with deep trench isolations and methods for producing the same

Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.

Isolation scheme for high voltage device

A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a fluorine implant region in the halo region of the first active region before or after formation of the drain and source extension and halo regions.

Methods for fabricating integrated circuits with the implantation of fluorine

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiOcap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Semiconductor device with reduced contact resistance and method of manufacturing thereof

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a nitrogen implant region in the halo region of the first active region after formation of the drain and source extension and halo regions.

Methods for fabricating integrated circuits with the implantation of nitrogen

One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed.

Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process

Growing community of inventors

Singapore, Singapore

Shiang Yang Ong