Intel Corporation

Shi-Ning Yang

Alan M Myers

Thomas A Letson

Peter K Charvat

Peng Bai

Timothy L Deeter

Melton C Bost

Robert A Gasser

A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.

Guard wall to reduce delamination effects within a semiconductor die

A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

Via hole profile and method of fabrication

Anchored via connection

Method of forming a guard wall to reduce delamination effects

Growing community of inventors

Portland, OR, United States of America

Shi-Ning Yang