United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Shi-Chung Sun

Hien-Tien Chiu

Tsai-Fu Chen

Lin-Sung Wang

Ming-Hsing Tsai

A new method of forming a molybdenum nitride barrier layer by chemical vapor deposition from the precursor bisdiethylamido-bistertbutylimido-molybdenum (BDBTM) as a diffusion barrier for copper metallization is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the sermiconductor device structures. A via opening is etched through the insulating layer to contact one of the semiconductor device structures. A barrier layer of molybdenum nitride is conformally deposited by chemical vapor deposition within the via. A layer of copper is deposited overlying the molybdenum nitride barrier layer wherein the molybdenum nitride barrier layer prevents copper diffusion to complete the copper metallization in the fabrication of an integrated circuit device.

MOCVD molybdenum nitride diffusion barrier for CU metallization

A new method of forming a molybdenum nitride barrier layer by chemical vapor deposition from the precursor bisdiethylamido-bistertbutylimido-molybdenum (BDBTM) as a diffusion barrier for copper metallization is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor devise structures. A via opening is etched through the insulating layer to contact one of the semiconductor device structures. A barrier layer of molybdenum nitride is conformally deposited by chemical vapor deposition within the via. A layer of copper is deposited overlying the molybdenum nitride barrier layer wherein the molybdenum nitride barrier layer prevents copper diffusion to complete the copper metallization in the fabrication of an integrated circuit device.

MOCVD molybdenum nitride diffusion barrier for Cu metallization

A process for fabricating electrodes for the capacitor dielectric of semiconductor memory devices with low leakage current characteristics is disclosed. The process comprises the steps of first depositing a titanium oxide film over a semiconductor silicon substrate. The deposited titanium oxide film is then annealed. A layer of tungsten nitride top electrode is then deposited on the annealed titanium oxide film. A second annealing procedure is then conducted to simulate post electrode high temperature process.

Process for fabricating low leakage current electrode for LPCVD titanium

Composite TiO.sub.2 /Ta.sub.2 O.sub.5 films by in-situ sequential CVD deposition are presented for a storage capacitor of a three-dimensional cell in DRAM applications. The capacitor with the Ta.sub.2 O.sub.5 /TiO.sub.2 /Ta.sub.2 O.sub.5 alternating layer structure has comparable leakage current density and higher capacitance per unit area as compared to a capacitor with Ta.sub.2 O.sub.5 and TiO.sub.2 single layer structures.

Composite dielectric films

A process for fabricating a tantalum nitride diffusion barrier for the advanced copper metallization of semiconductor devices is disclosed. The process comprises the steps of first preparing a semiconductor device fabricated over the surface of a silicon substrate having a component with a fabricated contact opening. Before the formation of the copper contact by deposition, the process performs a tantalum nitride low-pressure chemical-vapor-deposition procedure that deposits a layer of tantalum nitride thin film over the surface of the device substrate. After the copper deposition, a photoresist layer is subsequently fabricated for patterning the deposited copper contact and tantalum nitride layers, whereby the deposited thin film of tantalum nitride is patterned to form the thin film as the metallization diffusion barrier for the semiconductor device. The tantalum nitride low-pressure chemical-vapor-deposition procedure includes depositing a layer of tantalum nitride utilizing a metal-organic precursor terbutylimido-tris-diethylamido tantalum (TBTDET) in a cold-wall low pressure reactor with a base pressure of about 10.sup.-5 torr. The source of the metal-organic precursor is vaporized at a temperature of about 40.degree. to 50.degree. C. The typical deposition pressure is about 20 mtorr. Tantalum nitride layer of low carbon content and low resistivity may thus be formed in the disclosed chemical-vapor-deposition procedure having effective capability against copper diffusion.

Process for fabricating tantalum nitride diffusion barrier for copper

A process for fabricating dual-gate CMOS of semiconductor devices having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition in a rapid thermal reactor is disclosed. The process comprises the steps of first fabricating components of the dual-gate CMOS on a semiconductor silicon substrate. The dual-gate CMOS components includes P- and N-wells and source/drain regions formed in the silicon substrate. Gate oxide for the dual-gate CMOS is then grown. A thin nitrogen-doped polysilicon film is then deposited over the gates, and followed by the deposition of a undoped polysilicon film, which covers over the surface of the thin nitrogen-doped polysilicon film. Ions are then implanted into the dual-gates CMOS. In the process, the thin nitrogen-doped polysilicon film is deposited by introducing SiH.sub.4 and NH.sub.3 gas mixture into the rapid thermal reactor under a pressure of about 0.4 torr at about 750.degree. C. The thin nitrogen-doped polysilicon film has a thickness of about 60 .ANG.. The undoped polysilicon film is formed by deposition of SiH.sub.4 after the NH.sub.3 gas is evacuated from the rapid thermal reactor, and has a thickness of about 2,000 to 3,000 .ANG.. N.sub.2 O, NO and O.sub.2 gases may be utilized in the rapid thermal procedure for the formation of the oxide layer. Once the oxide layer is formed, the process of forming polysilicon may be continued in the reaction chamber without needing to be exposed to the ambient air. Contamination to the device is therefore avoided and the product yield rate improved. The rapid thermal reactor employed in the process is a load-locked single reactor.

Growing community of inventors

Taipei, Taiwan

Shi-Chung Sun