Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Sheng-Lin Hsieh

I-Chih Chen

Kuan Jung Chen

Chih-Mu Huang

Ching-Pei Hsieh

Ching-Pin Lin

Ting-Chun Kuan

Ru-Shang Hsiao

Fu-Tsun Tsai

Kuan-Jung Chen

A method of forming a semiconductor device structure includes forming a first resist structure over a hard mask. The method further includes patterning the first resist structure to form a trench therein. The method further includes performing a first hydrogen plasma treatment to the patterned first resist structure, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the trench. The method further includes patterning the hard mask using the patterned resist structure as an etch mask. The method further includes forming a second resist structure over the patterned hard mask. The method further includes patterning the second resist structure to form an opening therein. The method further includes performing a second hydrogen plasma treatment to the patterned second resist structure. The method further includes patterning the patterned hard mask using the patterned second resist structure as a second etch mask.

Trench etching process for photoresist line roughness improvement

A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.

Source/drain structure with barrier in FinFET device and method for forming the same

A semiconductor structure includes an active semiconductor fin having a first height, a dummy semiconductor fin adjacent to the active semiconductor fin and having a second height less than the first height, an isolation structure between the active semiconductor fin and the dummy semiconductor fin, and a dielectric cap over the dummy semiconductor fin. The dielectric cap is separated from the active semiconductor fin.

Structure having improved fin critical dimension control

A fin-type field effect transistor comprising a substrate, at least one gate stack, spacers and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins comprise channel portions and flank portions beside the channel portions, the flank portions and the channel portions of the fins are protruded from the insulators, the flank portions of the fins and the channel portions of the fins have substantially a same height from top surfaces of the insulators, and each of the flank portions of the fins has a top surface and side surfaces adjoining the top surface. The at least one gate stack is disposed over the substrate, disposed on the insulators and over the channel portions of the fins. The spacers are disposed on the side surfaces of the flank portions of the fins. The epitaxy material portions are located above the top surfaces of the flank portions of the fins.

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Taipei, Taiwan

Sheng-Lin Hsieh