United Microelectronics Corp.

Chung Shan Institute of Science and Technology, Armanents Bureau, M.n.d.

Sheng-Hsing Yang

Jyh-Kuang Lin

Ying-Tzung Wang

Jeng Gong

Kuan-Yu Fu

Chen-Chung Hsu

Mu-Chun Wang

Shing-Ren Sheu

Yih-Jau Chang

Yao-Chin Cheng

Sheng-Lung Chen

Chuan H Liu

Yu-Lin Su

Nai-Jen Yeh

Donald Cheng

Jyn-Kuang Lin

Jyh-Kung Lin

Shin-An Chen

Jiann-Shiun Torng

An embedded multi-functional preprocessing input data buffer comprises a clutter lock loop circuit, a multiplier, a mode selective multiplexer, a dual-port memory, an input multiplexer, self-testing circuit, decode circuit and an output multiplexer. The clutter lock loop and multiplication circuit selectively executes a coefficient multiplication or a clutter lock loop operation for the received data according to a working mode of the radar system. After receiving the data, the mode selective multiplexer may selectively output data processed by the clutter lock loop and multiplication circuit. The dual-port memory is coupled to the mode selective multiplexer for receiving and temporarily registering the data processed. The output multiplexer selectively outputs the data temporarily stored in the dual-port memory via a number of the output channels according to the working mode of the radar system.

Embedded multi-functional preprocessing input data buffer in radar system

A high-voltage lateral double-diffused metal oxide semiconductor has a field metal plate or an electrical field shield conductive layer, which is electrically coupled with a gate or a gate conductive layer that lies over a field oxide layer. A wire bridges over the field oxide layer and thus decreases the strength of the electrical field. The field oxide layer under the crossing wire has no drift region below. Therefore, the electrical field crowding effect does not occur at the junction between the drift region and the channel. In addition, there is no wire over the field oxide layer having the drift region below. Thus, the components can work normally. In this way, the strength of electrical field between the drift region and the channel decreaes and the breakdown voltage of high-voltage lateral double-diffused metal oxide semiconductor increases.

Method of fabricating a high-voltage lateral double diffused metal oxide semiconductor

A method for testing the reliability of a dielectric thin film. An exponential current ramp test is performed with a delay time to test the dielectric thin film. An exponential current ramp charge-to-breakdown distribution, which is represented by cumulative distribution failure percentage, is obtained. An exponential current ramp charge-to-breakdown at a cumulative distribution failure percentage is calculated. An exponential current ramp constant and a constant current stress constant at the cumulative distribution failure percentage are calculated. A constant current stress charge-to-breakdown at the cumulative distribution failure percentage is calculated by using a specified current density and the constant current stress constant at the cumulative distribution failure percentage. The constant current stress charge-to-breakdown at the cumulative distribution failure percentage is compared to a specified constant current stress charge-to-breakdown to determine the reliability of the dielectric thin film.

Reliability testing method of dielectric thin film

A method for measuring a capacitance of a passive device region. The passive device region is formed on a substrate having a conductive type different from that of the passive device region. Two bias voltages are applied to two terminals of the passive device region. By measuring the distance between these two terminals and the width of the passive device region, plus the grading coefficients of both area effect and sidewall effect, capacitance induced at both terminals can be derived.

Method for measuring capacitance of passive device region

A multi-layer metallization capacitive structure is provided to a conductive line, such as a power line or signal transmission line in an integrated circuit, where the undesired effect of simultaneous switching noise (SSN) is adverse due to rapid switching of pulses in a digital signal. The multi-layer metallization capacitive structure can help reduce the SSN effect in the integrated circuit by providing at least one metallization layer which extends substantially beneath the conductive line; and at least one dielectric layer sandwiched between the power line and the metallization layer. The multi-layer metallization capacitive structure has an optimal effect if the metallization layer is designed to be precisely equal in width to the power line. The multi-layer metallization capacitive structure has an advantage over the prior art in that it can be formed together with the processing for forming multiple interconnects in the integrated circuit without the need to devise additional processes. Moreover, it requires a reduced layout area to implement as compared to the conventional on-chip capacitor.

Multi-layer metallization capacitive structure for reduction of the simultaneous switching noise in integrated circuits

In one embodiment, the present invention is provided for higher BJT gain and more quality device. Providing a substrate incorporating a device, wherein the device is defined MOS region and BJT region. Conductivity-type well region is formed on the substrate, and then a gate oxide layer is formed on the conductivity-type well region of MOS region. Consequently, a polysilicon layer is deposited on the gate oxide layer of MOS region. Using photolithographic and etching process to define a gate, wherein the polysilicon layer is used as the gate of MOS region. Further implanting ions of a first conductive type into the substrate of MOS region. A first dielectric layer is forming on sidewall of the gate, wherein the first dielectric layer is used as a spacer of MOS region. Sequentially, a first photoresist layer is formed over substrate of BJT region to define an emitter of BJT. Then implanting second ions of the first conductive type into the substrate of MOS region to form source/drain regions by using said spacer as a mask. Simultaneously implanting second ions of the first conductive type into the substrate to form the emitter of BJT. Sequentially, a second photoresist layer is deposited over the device of the MOS region. Finally, implanting third ions of the first conductive type into the emitter of BJT inside the substrate.

Method of improving vertical BJT gain

The invention describes a method of fabricating the integration of high-voltage devices and low-voltage devices. The ion implantation steps for forming the isolation doping regions and the drafting doping regions in the high-voltage device are used to form simultaneously the anti-punch-through regions in the low-voltage device. The production of the integrated circuit is then finished with other process steps.

Method of fabricating integration of high-voltage devices and

The invention provides an ESD protection circuit, which is formed on a semiconductor substrate. There is at least one MOS transistor branches out at a place between an I/O port and an internal circuit. The MOS transistor includes a drain region, a source region, a gate oxide layer, and a gate electrode. The source and the drain regions are formed in the substrate and located on each side of the gate electrode. An insulating layer is formed over the substrate to cover the MOS transistor. A drain contact is formed in the insulating layer with a contact to the drain region of the MOS transistor so that the drain region can be coupled to the internal circuit through the drain contact. A source contact is formed in the insulating layer with a contact to the source region of the MOS transistor so that the source region can be coupled to the I/O port through the source contact. Several floating silicide blocks is located between the insulating layer and the substrate at the drain region. The silicide blocks are about evenly distributed within the drain region, and preferably distributed in a structure like grid nodes with a shift for the adjacent node row. The silicide includes self-aligned silicide.

Electrostatic discharge protection circuit

A method for forming high voltage devices is provided. A P-type semiconductor substrate is provided. An oxide layer is formed on the P-type semiconductor substrate. A first P-well and a second P-well are formed in the P-type semiconductor substrate. A first N-well is formed in the second p-well and a second N-well is formed in the first P-well. A field oxide layer on the second N-well and a gate oxide layer are formed on the P-type substrate. A polysilicon layer is formed and defined as a gate on the gate oxide layer across a portion of the field oxide layer and aportion of the first N-well. A source region is formed in the first N-well and a drain region is formed in the second N-well. A P.sup.+ -type doped region is formed between the substrate and the source region across a part of the first N-well within the second P-well.

Method for forming high voltage device

A high voltage device. A first-type semiconductor substrate having at least a gate formed thereon is provided. The high voltage comprises a second-type first diffusion region in the semiconductor region, a second-type second diffusion region within the first diffusion region, a second-type third diffusion region under the second diffusion region, a field oxide layer on a part of the second diffusion region, and a first-type source/drain region under a surface between the field oxide layer and the gate.

High voltage device

A method of forming high voltage device. A first type semiconductor having at least a gate formed thereon is provided. A first ion implantation with a second type dopant is performed to form a first diffusion region in the semiconductor substrate. An oxide layer is formed on the semiconductor substrate. A second ion implantation with the second type dopant is performed to form a second diffusion region within the first diffusion region. A silicon nitride layer is formed on the oxide layer, through which an opening penetrates to exposed the oxide layer. A third ion implantation with the second type dopant is performed using the silicon nitride layer as a mask to form a third diffusion region within the second diffusion region. Drive-in is performed to deepen the third diffusion region. The silicon nitride layer is removed. The exposed oxide layer is transformed into a field oxide layer. A fourth ion implantation with a first type dopant is performed to form a fourth diffusion region as a source/drain region within the second diffusion region under a surface between the field oxide layer and the gate.

Method of forming high voltage device

A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided. The method comprises forming a first masking layer on the surface of the substrate, providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first implant regions in the well on either side of a first central region in the well and in a set of second implant regions adjacent to the well on either side of a second central region adjacent to the well, formation of insulating structures over the first and second regions, forming gate oxide layers above the first and second central regions, forming a second masking layer on the surface of the substrate, providing openings in the masking layer and implanting dopant ions of a second polarity into the surface of the substrate in a set of second implant regions in the well on either side of a first central region in the well and in a set of fourth implant regions adjacent to the well on either side of a second central region adjacent to the well, and formation of conductive gate structures over the gate oxide layers.

Metal gate high voltage integrated circuit/process

A method provides for manufacturing an MOSFET semiconductor device with an array of semiconductor structures on a lightly doped semiconductor substrate. A mask is formed upon the substrate with openings therein. An oxide is formed in the semiconductor substrate. The oxide extends down into sunken regions in the substrate through the openings in the mask. The oxide is removed from the substrate opening the sunken regions in the substrate. Spacers are formed in the openings in the mask forming smaller openings in the spacers. Then, ions are introduced into the substrate below the sunken regions through the smaller openings to form channel stop regions. Then the spacers are removed. A second oxide is formed in the sunken regions.

Self isolation manufacturing method

A process for fabricating double well regions for a semiconductor device having a first well region of a first type and a second well region of a second type on the substrate is disclosed. The process comprises the steps of first implanting impurities of the first type into the substrate. Then a shielding layer covering the location designated for the first well region of the first type on the substrate is formed. Impurities of the second type are then implanted into the substrate at locations not covered by the shielding layer and designated for the formation of the second well region of the second type. Finally, the impurities of both the first and the second type are driven into a designated depth of the substrate by a heating process to form the first well region of the first type and the second well region of the second type.

Process for fabricating double well regions in semiconductor devices

A method of fabricating high-voltage diode device on a silicon substrate which includes a first region and a second region is provided. The first and second regions having a first contact and a second contact area respectively. First, a first protective layer is formed on the first and second contact areas. A second protective layer is formed on the first protective layer and a portion of the first region adjacent to the first contact area. Next. Halogen ions are implanted into the first and second regions by using the second protective layer as a mask. The second protective layer is removed to expose unimplanted portion of the first region. Then, the first and second regions are oxidized to form a field oxide layer by using the first protective layer as a mask, wherein the unimplanted portion of the first region has a relatively lower oxidation rate and thereby a stepped part of the field oxide layer is formed over the first region. After removing the first protective layer, a first electrode plate is formed on the first contact area and the stepped part of the field oxide layer. A dielectric layer is formed overlying the first electrode plate and the field oxide layer. Finally, a second electrode plate is formed on the second contact area and the dielectric layer, completing the fabrication of high-voltage diode device.

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Hsinchu, Taiwan

Sheng-Hsing Yang