Taiwan Semiconductor Manufacturing Comp. Ltd.

Sheng-Feng Liu

Chun-Wei Chang

Hsien Yu Tseng

Jiaw-Ren Shih

Szu-Lin Liu

Jhong-Sheng Wang

Amit Kundu

Chung-Hui Chen

Wei-Chih Chen

Chii-Ping Chen

Wen-Sheh Huang

Wan-Te Chen

Bi-Ling Lin

A system for evaluating a heat sensitive structure of an integrated circuit design including a memory for retrieving and storing integrated circuit design layout data, thermal data, process data, and one or more operational parameters, a processor capable of accessing the memory and identifying a target region having a nominal temperature T, a plurality of heat generating structures and/or heat dissipating structures having corresponding impact areas that encompass a portion of the target region, calculating the temperature increases and/or decreases in the target region as a result of thermal coupling between the target region and the heat generating structures and/or heat dissipating structures, and conducting one or more parametric evaluations of the target region at an adjusted evaluation temperature Tafter which a network interface transmits the result(s) of the parametric evaluation(s) for use in a design review.

Electromigration evaluation methodology with consideration of thermal and signal effects

An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

Electromigration evaluation methodology with consideration of both self-heating and heat sink thermal effects

A semiconductor device includes a substrate having a major surface. The semiconductor device includes a dielectric material having a uniform thickness on the major surface of the substrate. The semiconductor device includes a first plurality of fins extending from the major surface of the substrate, wherein each fin of the first plurality of fins has a first height from the major surface of the substrate. The semiconductor device includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, each fin of the second plurality of fins has a second height different from the first height.

Fin field effect transistor (FinFET) device having position-dependent heat generation

A system for evaluating a heat sensitive structure of an integrated circuit design including a memory for retrieving and storing integrated circuit design layout data, thermal data, process data, and one or more operational parameters, a processor capable of accessing the memory and identifying a target region having a nominal temperature T, first and second heat generating structures within a first impact range of the target region, calculating the temperature increases ΔTand ΔTin the target region as a result of thermal coupling between the target region and the first and second heat generating structures, and conducting one or more parametric evaluations of the target region at an adjusted evaluation temperature T=T+ΔT+ΔTafter which a network interface transmits the result(s) of the parametric evaluation(s) for use in a design review.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a resistive element over the substrate. The semiconductor device structure also includes a thermal conductive element over the substrate. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line, and the first imaginary line and the second imaginary line intersect at a center of the main surface.

Semiconductor device structure with resistive element

An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

A method for evaluating a heat sensitive structure involving identifying a heat sensitive structure in an integrated circuit design layout, the heat sensitive structure characterized by a nominal temperature, identifying a heat generating structure within a thermal coupling range of the heat sensitive structure, calculating an operating temperature of the first heat generating structure; calculating a temperature increase or the heat sensitive structure induced by thermal coupling to the heat generating structure at the operating temperature; and performing an electromigration (EM) analysis of the heat sensitive structure at an evaluation temperature obtained by adjusting the nominal temperature by the temperature increase induced by the heat generating structure.

A method of making a semiconductor device includes defining a first fin structure over a major surface of a substrate, wherein the first fin includes a first material. The method includes defining a second fin structure over the major surface of the substrate. Defining the second fin structure includes forming a lower portion of the second fin structure, closest to the substrate, having the first material, and forming an upper portion of the second fin structure, farthest from the substrate, having a second material different from the first material. The method includes forming a dielectric material over the substrate and between the first and second fin structures. The method includes removing the upper portion of the second fin structure, wherein removing the upper portion of the second fin structure includes reducing a height of the second fin structure to be less than a height of the first fin structure.

Method of making fin field effect transistor (FinFET) device

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

A semiconductor device including a substrate having a major surface. The semiconductor device further includes a dielectric material on the major surface of the substrate. The semiconductor device further includes a first plurality of fins extending from the major surface of the substrate, wherein the dielectric material surrounding each fin of the first plurality of fins has a first thickness. The semiconductor device further includes a second plurality of fins extending from the major surface of the substrate, wherein a first fin of the second plurality of fins is on a first side of the first plurality of fins, a second fin of the second plurality of fins is on a second side of the first plurality of fins opposite the first side, the dielectric material surround each fin of the second plurality of fins has a second thickness, and the second thickness is different from the first thickness.

An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.

A semiconductor apparatus including a substrate having a substrate major surface, a dielectric material on the substrate major surface and having a second major surface distanced from the substrate major surface, and a plurality of fins extending from the substrate major surface through the dielectric material where the plurality of fins includes a first subset of fins and a second subset of fins, the first subset of fins located closer to a center of the plurality of fins than the second subset of fins, and an amount of heat generated during operation of the semiconductor device by each fin of the first subset of fins is less than an amount of heat generated by each fin of the second subset of fins during operation of the semiconductor device.

Growing community of inventors

Taipei, Taiwan

Sheng-Feng Liu