Promos Technologies, Inc

Other

Sheng-Fen Chiu

Hsiao-Lei Wang

Jesse Chung

Chi-Long Chung

Joseph Wu

Chun-Lin Chen

J S Shiao

Chao-Chueh Wu

Jackie Ding

Eddie Chiu

In accordance with the objectives of the invention a new processing sequence is provided for the creation of a layer of ARC. A first layer of ARC is deposited over a supporting surface, a blanket etch is performed to the surface of the first layer of ARC, leaving any openings that have been created in the supporting surface essentially filled with ARC material. A second layer of ARC is next applied over the surface of the etched first layer of ARC, this second layer of ARC provides a layer of ARC that is of uniform thickness over the supporting surface. Steps of baking may be applied to each of the layers of ARC after these layers have been deposited or after the first layer of ARC has been etched.

Method to improve surface uniformity of a layer of arc used for the creation of contact plugs

A structure or a process of the via chain is employed to test the misalignment. The structure of the via chain includes a first via chain in the first direction and a second via chain in the second direction. Using the structure having the via chains in two different directions, the misalignment can be easily detected.

Structure and process of via chain for misalignment test

A method for manufacturing a deep trench capacitor, which includes forming a layer of silicon nitride over a silicon substrate, depositing a layer of borosilicate glass having a predetermined thickness over the layer of silicon nitride, patterning and defining the layer of borosilicate glass to expose two regions of the silicon substrate separated by a sacrificial mask, wherein the sacrificial mask includes the layer of borosilicate glass and the layer of silicon nitride, etching the two regions of the silicon substrate to form two trenches, wherein the predetermined thickness of the layer of borosilicate glass allows the sacrificial mask and a portion of the silicon substrate beneath the sacrificial mask to be removed, depositing a layer of silicon nitride on the sidewalls of the trenches, and depositing doped polysilicon into the trenches to form a single capacitor.

Method for forming a trench capacitor

A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si N ) uniformity for increasing process yields. The method utilizes a thicker pad Si N as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si N layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si N layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si N layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si N layer to provide a more reliable structure for further processing.

Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate

A method of forming a planar silicon nitride layer is disclosed. The method comprises: forming a pad oxide layer; forming a first nitride layer on the pad oxide layer; forming a stop layer on the first nitride layer; forming a second nitride layer on the stop layer; performing intermediate processes that damage the second nitride layer; removing the second nitride layer; removing the stop layer such that the first nitride layer remains as the planar silicon nitride layer.

Growing community of inventors

Taichung, Taiwan

Sheng-Fen Chiu