Applied Materials, Inc.

Sheng-Chin Kung

Benjamin Colombeau

Naomi Yoshida

Patricia M Liu

Shiyu Sun

Bingxi Sun Wood

Nam Sung Kim

Miao Jin

Hua Chung

Abhishek Dube

Johanes F Swenberg

Malcolm J Bevan

Kartik Ramaswamy

Yang Yang

Tza-Jing Gung

Yi-Chiau Huang

Joseph F AuBuchon

Xuebin Li

Steven C H Hung

Steven Lane

Travis Koh

Steven C Hung

Nattaworn Boss Nunta

Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

Horizontal gate-all-around device nanowire air gap spacer formation

Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Gate interface engineering with doped layer

Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.

Horizontal gate all around device nanowire air gap spacer formation

Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

Cap oxidation for FinFET formation

The present disclosure generally relates to devices having conformal semiconductor cladding materials, and methods of forming the same. The cladding material is a silicon germanium epitaxial material. The cladding material is capable of being deposited to a thickness which is less than cladding materials formed by conventional deposition/etch techniques.

Method of forming conformal epitaxial semiconductor cladding material over a fin field effect transistor (FINFET) device

Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.

Integrated semiconductor processing

The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

Embodiments described herein generally relate to plasma process apparatus. In one embodiment, the plasma process apparatus includes a plasma source assembly. The plasma source assembly may include a first coil, a second coil surrounding the first coil, and a magnetic device disposed outside the first and inside the second coil. The magnet enables additional tuning which improves uniformity control of the processes on the substrate.

Magnet configurations for radial uniformity tuning of ICP plasmas

Implementations described herein generally relate to methods and systems for depositing layer on substrates, and more specifically, to methods for forming boron or gallium-doped germanium on silicon-containing surfaces. In one implementation, a method of processing a substrate is provided. The method comprises exposing a substrate having an exposed silicon-germanium surface and an exposed dielectric surface to a pre-treatment process, selectively depositing a boron-doped or a gallium-doped layer on the exposed silicon-germanium surface and exposing the substrate to a post-treatment process.

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Milpitas, CA, United States of America

Sheng-Chin Kung