Taiwan Semiconductor Manufacturing Comp. Ltd.

Sheng-Chieh Liu

Tzu-Yang Wu

Chia-Hung Kao

Sheng-Liang Pan

Hsueh-Liang Chou

Ya-Wen Lee

Yuan-Bang Lee

Jeffery Chu

Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.

Method and system for wafer backside alignment

A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Method and device for wafer backside alignment overlay accuracy

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Taichung, Taiwan

Sheng-Chieh Liu