Industrial Technology Research Institute

Vanguard International Semiconductor Corporation

Shaw-Tzeng Hsia

Kuang-Chao Chen

Ching-Ying Lee

Haw Yen

Lai-Juh Chen

Chih-Cheng Liao

A method is disclosed for improved planarization and deposition of intermetal dielectric layers in semiconductor substrates. More specifically, the method involves the performance of specific process steps in-situ. That is, unlike in prior art, starting with cured spin-on-glass (SOG), the steps of SOG etchback and deposition of the intermetal dielectric PECVD, all take place sequentially in the same chamber and without a vacuum break. If not in the same chamber, then in the same load lock system. In this manner, it is shown that no longer does the SOG layer delaminate from the oxide layer. Furthermore, because the system is not exposed to moisture due to the absence of vacuum break, there is no adverse reaction when metal is deposited into the via holes. It is also shown that the behavior of SOG can be further improved when it is subjected to, after etchback, to argon sputter treatment, and/or oxygen plasma treatment in-situ, that is, without a vacuum break from the time the SOG etchback is performed to the time of depositing the next layer of PECVD oxide over the planarized surface. As a by-product of the steps enumerated above, the disclosed method also reduces the contact resistance of metal interfaces in via holes.

In-situ SOG etchback and deposition for IMD process

A process, to fill small diameter contact holes with tungsten, without deleterious attack of contact hole liner materials, during the tungsten deposition, has been developed. The process consists of using a titanium nitride barrier layer, overlying a titanium adhesive layer. However the barrier characteristics of titanium nitride are enhanced by subjecting this layer to an anneal cycle in an nitrogen ambient. The annealing produces a more robust barrier in terms of incorporating additional nitrogen into the deposited titanium nitride layer, as well as forming titanium nitride on any underlying titanium, that may be exposed due to defects in the deposited titanium nitride layer.

Optimized tungsten contact plug process via use of furnace annealed

A process has been developed in which small diameter contact holes can be filled with chemically vapor deposited tungsten, without severe attack of the contact hole liner materials. An adhesive layer of titanium, and a barrier layer of titanium nitride are used for the contact hole liner, and are deposited prior to tungsten process. A process consisting of subjecting the barrier layer of titanium nitride to a rapid thermal anneal, in an ammonia ambient, results in enhanced barrier characteristics. The robust titanium nitride layer is now able to survive the tungsten deposition process, and attack form fluorine ions, produced during the decomposition of the tungsten source, tungsten hexafluoride.

Annealing of titanium - titanium nitride in contact hole

A process has been developed that allows small diameter contact holes to be filled with chemical vapor deposited tungsten, without tungsten peeling from the sides of the contact hole. The process consists of initially depositing an adhesive layer of titanium in the contact hole, followed by a rapid thermal anneal cycle, in an ammonia ambient, for purposes of creating a thin, uniform, barrier layer of titanium nitride. The titanium nitride protects the underlying titanium adhesion layer from the by-products introduced during the tungsten deposition, specifically the evolution of fluorine ions resulting from the decomposition of tungsten hexafluoride.

Nitridation of titanium, for use with tungsten filled contact holes

A new method for forming a planarized dielectric layer on a patterned conducting layer was accomplished. The method involves forming a insulating layer over a semiconductor substrate having semiconductor devices and elevated areas, created by an array of DRAM storage cells, formed therein. A metal conducting layer is deposited and then patterned by etching. The patterned conducting layer is used to make the electrical connections to the device contact. A barrier insulator is deposited on the patterned conducting layer and then a spin-on-glass is deposited by several coatings to fill the recesses in the patterned conducting layer and planarize the surface. A two step etch back process is then used to further planarize the layer and remove the spin-on-glass from the conducting layer surface. The process is designed to avoid over etching into the patterned conducting layer at the edges of the elevated regions of the DRAM, where the spin-on-glass is by its very nature thin.

Two step etch back spin-on-glass process for semiconductor planarization

A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via combining TEOS with ozone silicon oxide pyrolytic deposition with plasma-enhanced deposition processes and spin-on-glass processes. A first insulator layer is provided over the conductive layer by plasma-enhanced chemical vapor deposition (PECVD). This insulator layer is covered with a layer of TEOS with ozone deposited silicon oxide by pyrolytic chemical vapor deposition (THCVD). The TEOS with ozone silicon oxide layer will fill the irregular trenches and holes in the conductive layer structure not filled by the first insulator layer. The TEOS with ozone layer is anisotropically etched back leaving the TEOS with ozone layer only in the trenches and holes of the layer structure. A second insulating layer is deposited by PECVD and then is covered by at least one spin-on-glass layer to fill the wider valleys of the irregular structure. The spin-on-glass layer is cured, then partially blanket anisotropically etched through its thickness to the underlying second oxide layer at its highest points and leaving the spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

Inter-metal-dielectric planarization process

A passivation layer is provided over a conductive layer for contacting the active elements of semiconductor device structures in and on a semiconductor substrate. The passivation and conductive layers are patterned simultaneously. A thin oxide layer is deposited over the patterned conductive and passivation layers. The thin oxide layer is covered with a spin-on-glass layer to fill the valleys of the patterned conductive and passivation layers. The spin-on-glass layer is cured and then partially blanket anisotropically etched through its thickness and through the thin oxide layer to the underlying passivation layer at its highest point leaving spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization. Alternatively, an anisotropic oxide is deposited over patterned conductive lines of an integrated circuit. This anisotropic oxide deposits preferentially on the horizontal surfaces and relatively little on the vertical surfaces. The anisotropic oxide layer is covered with a spin-on-glass layer to fill the valleys of the patterned conductive layer. The spin-on-glass layer is cured and then partially blanket anisotropically etched through its thickness to the underlying anisotropic layer at its lowest point leaving spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

Submicron planarization process with passivation on metal line

A new method of metallization of an integrated circuit is described. This method can be used for a first metallization to contact the semiconductor substrate regions or for a subsequent metallizations for interconnection within the integrated circuit. An insulating layer is provided over the surface of a semiconductor substrate or over a metallization layer. At least one contact opening is made through the insulating layer to the semiconductor substrate or to the metallization layer. A barrier metal layer is deposited over the surface of the substrate and within the contact opening wherein most of the barrier metal is deposited on the bottom of the contact opening rather than on the sides of the opening. A metal layer is cold sputtered over the barrier metal layer, then the metal is hot sputtered over the cold-sputtered metal layer wherein the cold and hot sputtering are continuous operations to complete the metallization of the integrated circuit.

Aluminum plug process

A new method of completing a tungsten contact is described. An insulator layer is formed over device structures in and on a semiconductor substrate. The insulator layer is flowed to planarize the layer. The insulator layer is covered with a spin-on-glass layer which is baked and cured. Contact openings are formed through the insulator and spin-on-glass layers to the device structures and to the substrate. A nucleation layer is formed over the spin-on-glass layer and within the contact openings. A layer of tungsten is deposited over the nucleation layer. The tungsten layer is etched back, thereby leaving the tungsten layer within the contact openings and leaving some of the tungsten layer as residue overlying the spin-on-glass layer. The spin-on-glass layer is removed, thereby removing any tungsten layer residue overlying the spin-on-glass layer. The contacts are completed by an aluminum metalization.

Blanket tungsten etchback process using disposable spin-on-glass

A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via an integration of siloxane partial etchback and silicate processes. A first intermetal dielectric layer, thinner than that in conventional partial etchback methods, is deposited. This is covered with a siloxane spin-on-glass layer with no voids. This layer is baked, but not cured. The siloxane is partially etched back to the underlying metal layer resulting in a loss of planarity. An undoped silicate spin-in-glass coating is applied and baked followed by the curing of both the siloxane and silicate spin-on-glass layers. This results in excellent planarity with no cracking of the cured spin-on-glass. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size.

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Taipei, Taiwan

Shaw-Tzeng Hsia