Taiwan Semiconductor Manufacturing Comp. Ltd.

Shaulin Shue

Chung-Liang Chang

Chen-Hua Douglas Yu

Mei-Yun Wang

Shun-Liang Hsu

Chien-Hsueh Shih

ChaoChieh Tsai

Ming Hsing Tsai

Electrochemical plating polymer additives and method which reduces metal overburden in an electroplated metal while optimizing gap fill capability are disclosed. The polymer additives are provided in an electrochemical plating bath solution and may include low cationic charge density co-polymers having aromatic and amine functional group monomers. The low cationic charge density polymers may include benzene or pyrollidone functional group monomers and imidazole or imidazole derivative functional group monomers.

ECP polymer additives and method for reducing overburden and defects

A method of forming a copper structure, comprising the following steps. A substrate is provided. A patterned dielectric layer is formed over the substrate with the patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A Sn layer is formed directly upon the exposed sidewalls of the opening. A copper seed layer is formed upon the Sn layer within the opening. A bulk copper layer is formed over the copper seed layer, filling the opening. The structure is thermally annealed whereby Sn diffuses from the Sn layer into the copper seed layer and the bulk copper layer forming CuSn alloy within the copper seed layer and the bulk copper layer.

Copper electromigration inhibition by copper alloy formation

A method of forming an oxide free copper interconnect, comprising the following steps. A substrate is provided and a patterned dielectric layer is formed over the substrate. The patterned dielectric layer having an opening exposing a portion of the substrate. The opening having exposed sidewalls. A copper seed layer is formed over the sidewalls of the opening. The copper seed layer is subjected to an electrochemical technique to eliminate any copper oxide formed over the copper seed layer. A bulk copper layer is electrochemically plated over the copper-oxide-free copper seed layer, filling the opening and forming the oxide-free copper interconnect.

Technique to enhance the yield of copper interconnections

A method for forming a damascene structure over tungsten plugs using nitridation of said tungsten plugs to provide better oxidation resistance, better adhesion properties and better copper diffusion barrier proerties. The process begins by providing a substrate structure having at least one device layer thereon and having a first dielectric layer overlying the device layer. The dielectric layer has tungsten plugs therein providing a conductive path between the surface of the dielectric layer and the device layer. The tungsten plugs are nitriduzed to form a WN,layer on top of the tungsten plugs. A second dielectric layer is deposited over the WNx layer and the first dielectric layer. The second dielectric layer is patterned to form a trench in the second dielectric layer; whereby the WN,layer is exposed in the trench. A barrier layer is formed in the trench. A metal layer is formed over the barrier layer. The metal layer and the second dielectric layer are planarized to form a damascene structure.

Method for forming a copper damascene structure over tungsten plugs with improved adhesion, oxidation resistance, and diffusion barrier properties using nitridation of the tungsten plug

Methods are disclosed to provide a low-cost method of producing a refractory liner in submicron vias or trenches applying ionized metal plasma using physical vapor deposition (PVD). The refractory liner is deposited on the bottom and sidewalls of the submicron vias and trenches in a two step PVD, using first high pressure and then low pressure. By selecting adhesion layer and diffusion barrier materials such as tantalum, tantalum nitride or titanium nitride or alloys of these metals a uniform barrier is created which forms a suitable layer around copper metallization.

Multi-step deposition to improve the conformality of ionized PVD films

A method for forming a titanium nitride layer within an integrated circuit. There is first provided a substrate. There is then formed over the substrate a virgin titanium nitride layer, where the virgin titanium nitride layer is formed through a chemical vapor deposition (CVD) method employing a tetrakis-diallylamido titanium source material without a halogen activator source material. The virgin titanium nitride layer is then annealed in a first plasma comprising nitrogen and hydrogen to form a refined titanium nitride layer. The refined titanium nitride layer is then annealed in a second plasma comprising nitrogen without hydrogen. Through the method there is formed a titanium nitride layer with superior step coverage, low resistivity and low impurities concentration.

Multi-step plasma treatment process for forming low resistance titanium

A method for improving the source/drain resistance in the fabrication of an integrated circuit device is described. Gate electrodes are formed on the surface of a semiconductor substrate. Lightly doped regions are implanted into the semiconductor substrate using the gate electrodes as a mask. First spacers are formed on the sidewalls of the gate electrodes. Second spacers are formed on the sidewalls of the first spacers. Heavily doped source and drain regions are implanted into the semiconductor substrate using the gate electrodes and first and second spacers as a mask. Thereafter, the second spacers are removed. A titanium layer is deposited by chemical vapor deposition over the substrate whereby titanium silicide is formed overlying the gate electrodes and overlying the source and drain regions and whereby elemental titanium is deposited overlying the first spacers wherein the titanium silicide overlying the source and drain regions improves the source/drain resistance. The elemental titanium is removed. The substrate is annealed to transform all of the silicide into C54-phase TiSi.sub.2 and the fabrication of the integrated circuit device is completed.

Method of fabricating MOSFET devices

A method of forming a titanium nitride barrier layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. A titanium glue layer is deposited overlying the insulating layer and within the opening. A titanium nitride barrier layer is deposited overlying the titanium glue layer by chemical vapor deposition. A first metal layer is deposited overlying the barrier layer and filling the opening. The first metal layer is etched back leaving the first metal layer only within the opening whereby a portion of the titanium glue layer is exposed. Thereafter, the substrate is annealed to form a titanium nitride protection layer on the exposed portion of the titanium glue layer. Thereafter, the substrate is cleaned wherein the protection layer prevents oxidation of the titanium glue layer. A second metal layer is deposited overlying the first metal layer and patterned to complete the metallization in the fabrication of an integrated circuit device.

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Hsinchu, Taiwan

Shaulin Shue