Globalfoundries Inc.

International Business Machines Corporation

University of California

Shariq Siddiqui

Frank Wilhelm Mont

Brown Cornelius Peethala

Douglas M Trickett

Mark L Lenhardt

Jessica P Striss

Tenko Yamashita

Hiroaki Niimi

Rohit Galatage

Xunyuan Zhang

Cornelius Brown Peethala

Bhagawan Sahu

Han You

Christopher J Penny

Hoon Sik Kim

Yann Mignot

Jinping Liu

Jiehui Shu

Roger Allan Quon

Vimal Kumar Kamineni

Nicholas V Licausi

Naomi Yoshida

Andrew C Kummel

David Paul Brunco

Randolph F Knarr

Jeremy Austin Wahl

Adam Brand

Lisa F Edge

Gangadhara Raja Muthinti

Pei Liu

Tobin Kaufman-Osborn

Kasra Sardashti

Kevin J Ryan

Tyler Kent

Chung-Ju Yang

Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one self-aligned via within at least dielectric material; plugging the at least one self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

Chamferless via structures

Chamferless via structures and methods of manufacture are provided. The method includes: forming at least one non-self-aligned via within at least dielectric material; plugging the at least one non-self-aligned via with material; forming a protective sacrificial mask over the material which plugs the at least one non-self-aligned via, after a recessing process; forming at least one trench within the dielectric material, with the protective sacrificial mask protecting the material during the trench formation; removing the protective sacrificial mask and the material within the at least one non-self-aligned via to form a wiring via; and filling the wiring via and the at least one trench with conductive material.

An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

One illustrative method disclosed includes, among other things, forming a first dielectric layer and forming first and second conductive structures comprising cobalt embedded in the first dielectric layer. A second dielectric layer is formed above and contacting the first dielectric layer. The first and second dielectric layers comprise different materials, and a portion of the second dielectric layer comprises carbon or nitrogen. A first cap layer is formed above the first and second conductive structures and the second dielectric layer.

Methods of mitigating cobalt diffusion in contact structures and the resulting devices

The present disclosure generally relates to semiconductor structures and, more particularly, to metal insulator metal capacitor devices and methods of manufacture. The method includes: depositing a bottom plate; depositing a dielectric film over the bottom plate; exposing the dielectric film to a gas; curing the dielectric film; and depositing a top plate over the dielectric film.

Metal insulator metal capacitor devices

A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.

Active gate contacts and method of fabrication thereof

Structures for reliability caps used in the manufacture of a field-effect transistor and methods for forming reliability caps used in the manufacture of a field-effect transistor. A layer comprised of a metal silicon nitride is deposited on a high-k dielectric material. The high-k dielectric material is thermally processed in an oxygen-containing ambient environment with the layer arranged as a cap between the high-k dielectric material and the ambient environment. Due at least in part to its composition, the layer blocks transport of oxygen from the ambient environment to the high-k dielectric material.

Reliability caps for high-k dielectric anneals

In an embodiment, a method comprises fitting a spectroscopic data of a layer in a layered structure to a dielectric function having a real part and an imaginary part; confirming that the dielectric function is physically possible; based on the dielectric function not being physically possible, repeating the fitting the spectroscopic data, or, based on the dielectric function being physically possible, defining an n degree polynomial to the dielectric function; determining a second derivative and a third derivative of the n degree polynomial; equating the second derivative to a first governing equation and the third derivative to a second governing equation and determining a constant of the first governing equation and the second governing equation; and based on the key governing equations, determining one or more of a band gap, a thickness, and a concentration of the layer.

Method for characterization of a layered structure

Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S&#x2014;H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200&#xb0; C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200&#xb0; C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Low temperature atomic layer deposition of oxides on compound semiconductors

Aspects of the present disclosure provide a method of cleaning a semiconductor device. The method includes providing a semiconductor wafer having an exposed cobalt surface and rinsing the exposed cobalt surface with cathode water having a pH greater than 9 and an oxidation reduction potential of less than 0.0.

Method of cleaning semiconductor device

Growing community of inventors

Albany, NY, United States of America

Shariq Siddiqui