Texas Instruments Corporation

Pdf Solutions, Incorporated

Sharad Saxena

Purnendu K Mozumder

Richard Gene Burch

Joseph C Davis

Karthik Vasanth

Suraj Rao

Yuan Yu

Chenjing L Fernando

Carlo Guardiani

Patrick D McNamara

Tomasz Brozek

Meindert Martin Lunenborg

Lidia Daldoss

Mike Kyu Hyon Pak

Christopher Hess

Larg H Weiland

Rakesh Vallishayee

Kelly Jay Taylor

Philip D Schumaker

Gregory Boyd Shinn

E Ajith Amerasekera

Christoph Dolainsky

Michele Quarantelli

Pushkar Prabhakar Apte

Shiying Xiong

Hossein Karbasi

Amy J Unruh

Alberto Piadena

Thomas Brozek

Andrei Shibkov

William W Pu

Jianjun Cheng

Dale Coder

Jae-Yong Park

Shian-Wei Aur

Benjamin Shieh

Mark Spinelli

A novel system for in-product Bias Temperature Instability (BTI) characterization that allows for characterization of transistor degradation rates is disclosed; it is self-testing and can be embedded in real products without impacting the host functionality. The test data collected during product chip testing (at Electrical Wafer Sort) can be used for identification of abnormal material and for material disposition, or to predict the chip aging rate and premature failure risk due to BTI degradation. The system can also collect the data from the real time device aging in the field, during the host chip operational lifetime. The system is equipped with local programmable power supply generation and self-test capabilities to allow concurrent operations with the host application. The Devices Under Test (DUTs) consist of standard cell-based Ring Oscillators (ROs) which have the unique capability of decoupling the BTI effects on N-type and P-type MOSFET transistors. New switching circuitry is implemented that provides for minimal delay between the stress and measurement phases, thus giving the system the capability of fully characterizing the BTI relaxation dynamic.

Embedded system to characterize BTI degradation effects in MOSFETs

Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

Described is a CBCM technique that works only with PMOS transistors or only with NMOS transistors. Specifically, a method of monitoring performance of an integrated circuit device using a CBCM technique is disclosed, the method comprising: providing a metrology structure having a pseudo-inverter comprising a pull-up pull-down transistor switch, wherein the transistor switch comprises a pull-up transistor and a pull-down transistor of the same type; charging and discharging a device under test (DUT) coupled to the pseudo-inverter using a non-overlapping clock; measuring capacitance of the DUT with a gate voltage of the pull-up transistor at a preset value; and, using the value of the measured capacitance to estimate a dimension of a structure in the integrated circuit device. The non-overlapping clock is generated by: turning the pull-down transistor off when the pull-up transistor is on; and, turning the pull-down transistor on when the pull-up transistor is off.

Method for applying charge-based-capacitance-measurement with switches using only NMOS or only PMOS transistors

Methods of measuring fin height electrically for devices fabricated using FinFET technology are disclosed here. One method uses an interleaving comb-like test structure with no gate. The other method extracts fin height from total gate capacitance from FinFETS with varying gate lengths. When a comb-like structure with no gate is used to measure fin height, if there is another structure with a gate is used, then the gate capacitance may be measured to independently measure thickness of gate dielectric.

Test structures and method for electrical measurement of FinFET fin height

Disclosed are methods for measuring capacitance in presence of leakage in integrated circuits. In particular, it teaches a method of measuring leaky capacitors using charge based capacitance measurement (CBCM) technique taking into account parasitic resistance. Fast and accurate measurement of capacitances allows the estimation of a number of technology parameters like: gate-dielectric thickness, gate critical dimension, trench depth in a damascene metallization process, height of a fin in a Fin FET device etc.

Method for accurate measurement of leaky capacitors using charge based capacitance measurements

Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies

Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.

Systems and methods for detecting and monitoring nickel-silicide process and induced failures

A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.

Method for reducing layout printability effects on semiconductor device performance

A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

Method for optimizing the characteristics of integrated circuits components from circuit specifications

A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores

A computer implemented method for statistical modeling and simulation of the impact of global variation and local mismatch on the performance of integrated circuits, comprises the steps of: estimating a representation of component mismatch from device performance measurements in a form suitable for circuit simulation; reducing the complexity of statistical simulation by performing a first level principal component or principal factor decomposition of global variation, including screening; further reducing the complexity of statistical simulation by performing a second level principal component decomposition including screening for each factor retained in the first level principal component decomposition step to represent local mismatch; and performing statistical simulation with the joint representation of global variation and local mismatch obtained in the second level principal component decomposition step.

Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits

An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design ( ) and a specified set of fabrication process conditions ( ), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap ( ) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.

Method and apparatus for predicting an operational lifetime of a transistor

Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.

Integrating dual supply voltages using a single extra mask level

A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at the output terminals of the at least one RSM model and experimental data. The objective function is optimized in an optimizer and the optimized objective function is fed to the input terminal of the RSM. Building of at least one RSM model includes establishing a range for the simulation, running a simulation experiment for the designed experiment, extracting relevant data from said experiment and building the RSM model from the extracted relevant data. The step of running a simulation experiment comprises the step of running a DOE/Opt operation. The objective function is, for example, the square root of the sum of the squares at all of the differences between the target values and the observed values at all points being investigated. The optimizing in the optimizer is preferably a gain function which adjusts the parameters to the input based upon the error signal to minimize the error signal.

Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators

Method for adequately modeling process induced variabilities is disclosed that comprises the steps of acquiring experimental data and defining a particular design space. Values for the mean and standard deviation of the experimental data at each of the points defining the design space are calculated. The experimental values of the output parameters at each of the design points is normalized to extract the shape of the distribution of each of the design points. The normalized values are then merged to form a cumulative distribution function associated with the data. The cumulative distribution function is applied to a new design point in a predicted fashion by first calculating a mean and standard deviation value for the new point by interpolating from the mean and standard deviation values from the experimental data. The cumulative distribution function is then scaled and centered using the interpolated mean and standard deviation values to provide a predicted data distribution for the new design point.

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Richardson, TX, United States of America

Sharad Saxena