Chartered Semiconductor Manufacturing Ltd (corporation)

Shao Kai

Sanford Chu

Chit Hwei Ng

Ng Chit Hwei

Jia Zhen Zheng

Lup San Leong

Chaw Sing Ho

Daniel Yen

Sia Choon Beng

Xing Yu

Raymond Joy

Chen Liang

Sajan Marokkey Raphael

Chew Kok Wai

Cheng-Wei Hua

Tjoa Tjin Tjin

Bao Guang Wen

Wu-Guan Ping

Methods for forming a metal-insulator-metal (MIM) capacitor using an organic anti-reflective coating (ARC) are described. The first electrode of the MIM capacitor is formed from a first metal layer. The organic ARC is applied, and the second electrode of the MIM capacitor is formed from a second metal layer. The organic ARC is then removed using a nominal clean technique. Because the organic ARC is removed, the performance of the MIM capacitor is improved. Specifically, the breakdown voltage of the MIM capacitor increases and the leakage current decreases.

Method for forming a MIM (metal-insulator-metal) capacitor

A first and second damascene copper interconnect plug are created over the surface of a substrate. A MIM capacitor, which is aligned with the second damascene copper interconnect plug, is created by a one-time etch of a stack of layers comprising Ta/capacitor dielectric/Ta. Copper interconnects are then created aligned with the MIM capacitor and the second damascene interconnect plug.

Metal sandwich structure for MIM capacitor onto dual damascene

An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing. In addition, the method of forming the MIM capacitors, described herein, can also be used to form anti-fuse devices, in field-programmable gate arrays, FPGA.

MIM and metal resistor formation at CU beol using only one extra mask

A method of fabricating high quality passive components having reduced capacitive and magnetic effects by using a Schottky diode underlying the passive components in the manufacture of integrated circuits is described. A Schottky diode is formed completely covering an active area where passive devices are to be formed. The Schottky diode is covered with a dielectric layer. Passive components are formed overlying the dielectric layer wherein the Schottky diode reduces substrate noise resulting in high quality of the passive components.

Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components

A new processing sequence is provided for the creation of a MIM capacitor. The process starts with the deposition of a first layer of metal. Next are deposited listed, a thin layer of metal, a layer of insulation, a second layer of metal and a layer of Anti Reflective Coating. An etch is then performed to form the second electrode of the MIM capacitor (using the etch stop layer to stop this etch), MIM spacers are formed on the sidewalls of the second electrode of the MIM capacitor (also using the etch stop layer to stop this etch). The dielectric and first electrode of the MIM capacitor are formed by etching through the second layer of insulation and the first layer of metal. This is followed by conventional processing to create contact points to the MIM capacitor.

Darc layer for MIM process integration

A method for integrating the dual gate and double poly capacitor processes to fabricate an analog capacitor integrated circuit device is described. An isolation region is provided separating a first active area from a second active area in a semiconductor substrate. A first gate oxide layer is formed overlying the semiconductor substrate in both active areas. A first polysilicon layer is deposited overlying the first gate oxide layer and the isolation region. An capacitor dielectric layer comprising an oxide layer and a nitride layer is deposited overlying the first polysilicon layer. The capacitor dielectric layer and first polysilicon layer are etched away where they are not covered by a mask to form a first polysilicon gate electrode in the first area and a polysilicon capacitor bottom plate and overlying capacitor dielectric overlying the isolation region. The first gate oxide layer is removed in the second area and a thinner second gate oxide layer is formed in the second area. A second polysilicon layer is deposited overlying the second gate oxide layer, bottom capacitor plate and capacitor dielectric, and the first polysilicon gate electrode. The second polysilicon layer is etched away where it is not covered by a mask to form a second polysilicon gate electrode in the second area and to form a top capacitor plate overlying the bottom capacitor plate having the capacitor dielectric layer therebetween.

Dual gate and double poly capacitor analog process integration

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Singapore, Singapore

Shao Kai