Macronix International Co., Ltd.

Shao-Chung Hsu

Chih-Ping Chen

Ta-Hung Yang

Chen-Fu Chien

Cheng-Yi Lin

Mao-I Ting

Hsin-Cheng Liu

Yih-Cheng Shih

Jung-Kuei Lu

De-Chuan Liu

The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.

Critical dimension statistical process control in semiconductor fabrication

Conventionally, efforts to improve the yield of chips produced on a wafer focused on defect reduction. Another approach is optimizing wafer exposure patterns. The present invention includes a computer-based procedure and apparatus to expose cells on the surface of a wafer so as to maximize the number of dies produced from a wafer. The invention is useful in the exposure of six and eight inch wafers, as well as larger wafers.

Procedure of alignment for optimal wafer exposure pattern

Growing community of inventors

Hsinchu, Taiwan

Shao-Chung Hsu