Vanguard International Semiconductor Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Ememory Technology Inc.

Shao-Chang Huang

Chih-Hsuan Lin

Chieh-Yao Chuang

Yeh-Ning Jou

Chun-Chih Chen

Hwa-Chyi Chiou

Ching-Ho Li

Jian-Hsing Lee

Kai-Chieh Hsu

Jung-Tsun Chuang

Li-Fan Chen

Hsien-Feng Liao

Hung-Wei Chen

Ting-You Lin

Yu-Kai Wang

Gong-Kai Lin

Wei-Yao Lin

Ming-Hsiang Song

Chien-Wei Wang

Kun-Wei Chang

Tang-Lung Lee

Hsin-Ming Chen

Shine Chung

Wen-Hsin Lin

Yi-Hsun Wu

Geeng-Lih Lin

Tsung-Mu Lai

Jiann-Tseng Huang

Karuna Nidhi

Yu-Hung Chu

Jia-Rong Yeh

Chi-Hung Lo

Ching-Wen Chen

Kuo-Feng Yu

Jiaw-Ren Shih

Chih-Cherng Liao

Shih-Chen Wang

Tong-Chern Ong

Wen-Hao Ching

Ming-Chou Ho

Ching-Yi Hsu

Chien-Hsien Song

Hsiao-Ying Yang

Yu-Chen Wu

Shi-Hsiang Lu

Shu-Chuan Lee

Wen-Hao Lee

Chun-Hung Lu

Chiun-Chi Shen

Chi-Di An

Ching-Wen Wang

Chang-Min Lin

Ting-Yu Chang

Wei-Sung Chen

Wei-Shung Chen

Wen-Tsung Wang

Yin-Ting Lin

Fu-Chun Tseng

Mao-Shu Hsu

Nai-Lun Cheng

Chien-Chi Hsu

Cheng-Hsin Chuang

Yi-Han Wu

Pang-Chuan Chen

Shang-Chuan Pai

Wei-Chung Wu

Chun-Chien Tsai

Szu-Chi Chen

Yu-Chun Chang

Luan-Yi Yen

Lin-Fwu Chen

Sheng-Chih Chuang

Pei-Chun Yu

Han-Pei Liu

Yu-Yen Lin

A driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between first and second power terminals. The detection circuit generates a detection voltage at a detection node based on a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device with a back-to-back connection structure that is coupled between a bonding pad and a first node and controlled by the detection voltage to generate a driving voltage at the first node for controlling the power device. In response to an electrostatic discharge event occurring on the bonding pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.

Driving circuit

A semiconductor structure is provided. At least one first well region is disposed in a semiconductor substrate and has a first conductivity type. At least one gate of a transistor is disposed over the first well region and extends in a first direction. At least one second well region and at least one third well region are disposed on opposite sides of the first well region and extend in the first direction. The second and third well regions have a second conductivity type. A first shielding structure is disposed on at least one end of the gate and partially overlaps the first well region in a vertical projection direction. The first shielding structure is separated from the end of the gate. A bulk ring is disposed in the semiconductor substrate and surrounds the gate, the second well region, the third well region, and the first shielding structure.

Semiconductor structure with a gate and a shielding structure

An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.

Electrostatic discharge protection circuit

An ESD protection circuit includes a buffer circuit, a driving circuit, and a power-clamping circuit. The buffer circuit includes first and second transistors having a first conductivity type coupled in a cascade configuration between a first node and a first power supply node. A bonding pad is coupled to the first node. The drive circuit determines a state of at least one of the first and second transistors according to a control voltage. The drive circuit includes a third transistor having a second conductivity type, which is coupled between a second power supply node and a gate of the first transistor and is controlled by the control signal. The power-clamping circuit is coupled to the bonding pad and a gate of the third transistor at a second node. The control voltage is generated at the second node and determined by a voltage at the bonding pad.

A level shifter includes a level shifting circuit and a voltage tracking circuit. The level shifting circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to first and second voltage terminals, and tracks one with a lower level among voltages of the first and second voltage terminals to generate a control voltage. The level shifting circuit includes first and second N-type transistors. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.

Level shifter

An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes first, second, and third transistors and a discharge circuit. The first transistor has a first gate, a first drain coupled to the bonding pad, and a first source coupled to a first node. The second transistor has a second gate coupled to a power terminal, a second drain coupled to the first gate, and a second source coupled to a ground. The third transistor has a third gate coupled to the power terminal, a third drain coupled to the first node, and a third source coupled to the ground. The discharge circuit is controlled by a driving voltage at the first node. In response to an electrostatic discharge event occurring on the bonding pad, the discharge circuit provides a discharge path between the bonding pad and the ground according to the driving voltage.

Electrostatic discharge protection circuit and electronic circuit

A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Voltage tracking circuits with low power consumption and electronic circuits using the same

A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

Semiconductor structure

An electrostatic discharge (ESD) protection circuit including a detection circuit, a voltage-divider element, and a discharge element is provided. The detection circuit is coupled between a first power line and a second power line. In response to an ESD event, the detection circuit enables a turn-on signal. The voltage-divider element is coupled between the first power line and a third power line and receives the turn-on signal. The discharge element is coupled between the second and third power lines. In response to the turn-on signal being enabled, the first discharge element discharges an ESD current.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.

Semiconductor device structure comprising source and drain protective circuits against electrostatic discharge (ESD)

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

Voltage tracking circuits and electronic circuits

A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are formed on the substrate. The first doped region is formed in the first well. The second doped region is formed in the second well. The gate electrode is disposed over the substrate. The gate electrode, the first doped region, and the second doped region constitute a transistor. The insulating layer is disposed on the substrate and overlaps the gate electrode. The field plate overlaps the insulating layer and the gate electrode. The tunable circuit provides either a first short-circuit path between the field plate and the gate electrode, or a second short-circuit path between the field plate and the first doped region.

Semiconductor structure and operation circuit

The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to first and second power bonding pads and detects whether an ESD event or an EOS event occurs at the first power bonding pad. The detection circuit controls a detection voltage on a detection node according to a detection result. The first and second power bonding pads belong to different power domains. The discharge circuit is coupled to the detection node and the first power pad. In response to the ESD event occurring at the first power bonding pad, the discharge circuit provides a discharge path between the first power bonding pad and a ground terminal according to the detection voltage. In response to the EOS event occurring at the first power bonding pad, the detection circuit activates a second discharge path between the first power bonding pad and the ground terminal.

Protection circuits

A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.

Protection circuit

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Hsinchu, Taiwan

Shao-Chang Huang