Qualcomm Incorporated

Shankarnarayan Bhat

Anand Bhat

Nishi Bhushan Singh

Ashutosh Anand

Praveen Raghuraman

Rajesh Kumar Tiwari

Nikhil Sudhakaran

Abhinav Kothiala

Sanjay Muchini

Arun Balachandar

Devadatta Bhat

A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.

Continuous write and read operations for memories with latencies

Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Method and apparatus for optimized memory test status detection and debug

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Bengaluru, India

Shankarnarayan Bhat