Rohm Gmbh

Chingis Technology Corporation

Rohn Gmbh

Shang-De Chang

Edwin Chow

Jia-Hwang Chang

Hsien-Wen Liu

Tzeng-Huei Shiau

Alex Wang

I-Sheng Liu

Han-Chih Lin

Jai-Hwang Chang

In a p-type flash memory array, separate programming and read bit lines are provided. The programming bit line is used only to program the floating gate transistors in the memory cells connected to that bit line. The read bit line is used only to read the state of a floating gate transistor in a selected memory cell connected to that bit line during the operation of the memory circuit. The resulting structure allows the use of low voltages during both programming and operation of the memory array. This makes possible the use of transistors in the memory array with feature sizes less than, for example, 0.18 microns. At the same time variable, unpredictable capacitances associated with each bit line in prior art p-type flash memory structures using comparable low programming voltages are eliminated when a particular memory cell attached to that bit line is being read out.

Low voltage low capacitance flash memory array

A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Nonvolatile memory solution using single-poly pFlash technology

A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.

Low voltage one transistor flash EEPROM cell using fowler-nordheim

Low voltage one transistor flash EEPROM cell using Fowler-Nordheim

Low voltage one transistor flash eeprom cell using fowler-nordheim

Growing community of inventors

Fremont, CA, United States of America

Shang-De Chang