Texas Instruments Corporation

Shane R Palmer

Thomas J Aton

Rajesh B Khamankar

John Neal Randall

Tsen-Hwang Lin

Akitoshi Nishimura

Yasutoshi Okuno

Jay M Brown

Steven C Gustafson

Carl Albert Vickery, Iii

Gong Chen

The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first target dimension. In one embodiment, the method comprises determining whether forming a phase pattern for the integrated circuit feature described in the design database will result in one or more phase blocks of the same phase type being positioned in relative proximity so as to result in a low contrast condition, selecting a second target dimension that will avoid the low contrast condition if the low contrast condition will result, and forming the phase pattern for an integrated circuit feature having the second target dimension. Systems for forming phase patterns and photomasks comprising the phase patterns of the present application are also disclosed.

Automated circuit design dimension change responsive to low contrast condition determination in photomask phase pattern

An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.

Optical proximity correction

A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.

Integrated circuit layout and verification method

An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell ( )). The cell can comprise a bitline contact ( ), storage node contacts ( ) hexagonally surrounding the bitline contact ( ), storage nodes ( ) also surrounding the bitline contact ( ), a wordline ( ) portions of which form field effect transistor gates. Large distances between bitline contacts ( ) and storage node contact ( ) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

Hexagonally symmetric integrated circuit cell

An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

A phase shift illuminator (700) is comprised of a light source (704) and a phase modulator (716), typically a flexure beam micromirror array, which transversely modulates the incident light beam. When a flexure beam micromirror array is used as the phase modulator (716) a polarizing beam splitter (712) and a quarter-wave plate (714) are used to separate the incident and reflected light beams. The phase modulated light beam (720) from the optical illuminator may be used in optical lithography by passing the light beam through a lithography mask (724), typically after the light beam is phase modulated, and focusing the light beam onto a target wafer (726).

Method of exposing a light sensitive material

Photolithographic technique and illuminator using real-time addressable

An optical lithography system (10) for exposing a layer (12) of radiation sensitive material on a semiconductor wafer (16) is provided. System (10) comprises a source of polarized radiant energy (18), a mask (20) and a lens (22). Radiant energy from a light source (28) is polarized in a predetermined orientation by polarization filter (30). Polarized radiant energy passes through mask (20) and exposes layer (12) in a predetermined pattern. Actuating member (32) may rotate polarization filter (30) to provide more than one orientation for the polarized radiant energy during a single exposure.

System and method for semiconductor processing using polarized radiant

A photolithographic mask or a directly written wafer has a pattern formed on a substrate 320. A grid pattern 316 and a layer of resist material 322 are formed on the substrate 320. The grid pattern 316 may be either above or beneath the resist material 320. The grid pattern 316 is scanned, by an e-beam or optical beam for example, without substantially reacting the resist layer 320 to obtain information on the location of the grid pattern 316. Portions of the resist material 320 are then exposed to form a device pattern. The device pattern is determined in part from the information and is also formed over the grid pattern 316. Other systems and methods are also disclosed.

Mask or wafer writing technique

A system (10) is provided for etching a surface (14). A vacuum enclosure (12) is provided to create a vacuum around containers (13) and the surface to be etched (14). A pressurized gas source (16) is utilized to input gas into the containers (13). A wire coil (38) is wrapped around the containers (13) and provided with an oscillator (40) to generate radio frequency energy. The radio frequency energy excites the gas within the containers (13) which is then discharged through an output opening (46) toward the surface to be etched (14). A vacuum pump (20) is provided to evacuate the enclosure (12).

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Dallas, TX, United States of America

Shane R Palmer