Intel Corporation

Shan Zhong

Weng Hong Teh

Robert L Sankman

John Stephen Guzek

Sairam Agraharam

Robert M Nickerson

Edvin Cetegen

Edward Rudolph Prack

Sandeep Razdan

Vipul V Mehta

Ziyin Lin

Nisha Ananthakrishnan

Yuying Wei

Sushrutha Reddy Gujjula

Chia-Pin Chiu

Wei Ey Li

Christopher L Rumer

Xavier Francois Brun

Anna M Prakash

Ching-Ping Janet Shen

Mark Saltas

Amanuel M Abebaw

Hsin-Wei Wang

Yang Guo

Olga Gorbounova

Soud Choudhury

Ifeanyi Okafor

Nai-Yuan Liu

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

Barrier structures for underfill containment

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.

Various embodiments disclosed relate to an assembly. The assembly includes a compound parabolic concentrator including an exit aperture that has a generally circular perimeter, which defines a circumference of the exit aperture. The assembly further includes a photodiode sensor generally that is aligned with the exit aperture of the compound parabolic concentrator. An optical adhesive layer adheres the exit aperture of the compound parabolic concentrator to the photodiode sensor. A protrusion extends between at least a portion of the perimeter of the compound parabolic concentrator exit aperture and the photodiode.

Compound parabolic concentrator including protrusion

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Semiconductor package having spacer layer

Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Interconnect structures with polymer core

Multi die package having a die and a spacer layer in a recess

A process of bumping a die backside includes opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, followed by filling the recess with a conductive material that contacts the TSV contact. Added solder is coupled to the conductive material at a level of the DBF. A subsequent die is coupled to the first die at the added solder to form an electrical coupling consisting of the TSV contact, the conductive material, and the added solder, an electrical bump coupled to the subsequent die. Apparatus and computer systems are assembled using the process.

Controlled solder-on-die integrations on packages and methods of assembling same

Growing community of inventors

Chandler, AZ, United States of America

Shan Zhong