General Electric Company

Apple Inc.

Shakti Singh Chauhan

Arun Virupaksha Gowda

Paul Alan McConnelee

Meng Chi Lee

Flynn P Carson

Hendrik Pieter Jacobus De Bock

Jun Chung Hsu

Stanton Earl Weaver, Jr

Tao Deng

Graham Charles Kirk

Tha-An Lin

Joo Han Kim

Jay Todd Labhart

Donald Paul Cunningham

Pramod Chamarthy

Brian Patrick Hoden

Stuart Connolly

David A Pakula

Daniel William Jarvis

Jun Zhai

Ian A Spraggs

Phillip R Sommer

Matthew Jeremiah Misner

Kaustubh Ravindra Nagarkar

Gregory N Stephens

Dennis R Pyper

Amir Salehi

Stanton Earl Weaver

James Neil Johnson

Derek J Walters

Ri-an Zhao

Alex J Crumlin

Yanfeng Chen

Shankar S Pennathur

David Shannon Slaton

Wenwu Zhang

Michael Victor Yeh

Faisal Razi Ahmad

Corey S Provencher

Binoy Milan Shah

Vu Thanh Vo

Christopher Michael Eastman

Arun Virupakska Gowda

Paul Alan Mcconnelee

Stanton Earl Weaver Jr

Jr Stanton Earl Weaver

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

Ultra-thin embedded semiconductor device package and method of manufacturing thereof

A system, such as a heat exchange assembly includes a support structure having a recess, a first support end, a second support end, and a support portion extending between the first and second support ends. The support structure further includes a plurality of projections protruding from a portion of a surface of the support structure, corresponding to the support portion. The support structure is a primary heat sink. The heat exchange assembly includes a vapor chamber having a casing and a wick disposed within the casing. The vapor chamber is disposed within the recess and coupled to a surface of the support structure such that the plurality of projections surrounds the vapor chamber. The casing includes a mid projected portion disposed at an evaporator portion of the vapor chamber. The first and second support ends, and the mid projected portion include a non-uniform surface configured to contact the circuit card.

Integrated heat exchange assembly and an associated method thereof

The present disclosure is related to printed circuit board packages and methods of assembly that may be used in the fabrication of electrical devices. Printed circuit board packages may be manufactured by stacking printed circuit board assemblies. Each printed circuit board assembly may have multiple printed circuit boards supported by a resin mold. The printed circuit board assemblies may be shaped to improve space utilization efficiency and to accommodate large electrical components that are attached to the printed circuit board package.

Stacked printed circuit board packages

Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

Substrate-less integrated components

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

Vertical interconnects for self shielded system in package (SiP) modules

A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Power overlay structure and method of making same

Electrical components may be packaged using system-in-package configurations or other component packages. Integrated circuit dies and other electrical components may be soldered or otherwise mounted on printed circuits. A layer of encapsulant may be used to encapsulate the integrated circuits. A shielding layer may be formed on the encapsulant layer to shield the integrate circuits. The shielding layer may include a sputtered metal seed layer and an electroplated layer of magnetic material. The electroplated layer may be a magnetic material that has a high permeability such as permalloy or mu metal to provide magnetic shielding for the integrated circuits. Integrated circuits may be mounted on one or both sides of the printed circuit. A temporary carrier and sealant may be used to hold the encapsulated integrated circuits during electroplating.

System-in-package devices with magnetic shielding

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Self shielded system in package (SiP) modules

A system and method for packaging light emitting semiconductors (LESs) is disclosed. An LES device is provided that includes a heatsink and an array of LES chips mounted on the heatsink and electrically connected thereto, with each LES chip comprising connection pads and a light emitting area configured to emit light therefrom responsive to a received electrical power. The LES device also includes a flexible interconnect structure positioned on and electrically connected to each LES chip to provide for control LES operation of the array of LES chips, with the flexible interconnect structure further including a flexible dielectric film configured to conform to a shape of the heatsink and a metal interconnect structure formed on the flexible dielectric film and that extends through vias formed in the flexible dielectric film so as to be electrically connected to the connection pads of the LES chips.

Overlay circuit structure for interconnecting light emitting semiconductors

A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Growing community of inventors

Niskayuna, NY, United States of America

Shakti Singh Chauhan