International Business Machines Corporation

Shaji Farooq

Kathleen Ann Stalter

John Ulrich Knickerbocker

Peter Jeffrey Brofman

Sudipta Kumar Ray

Rao Venkateswara Vallabhaneni

Govindarajan Natarajan

Lester W Herron

Raymond A Jackson

Donald Rene Wall

Srinivasa S Reddy

Mark G Courtney

Gregory Blair Martin

Vivek M Sura

Sampath Purushothaman

Hilton T Toy

Frank Louis Pompeo

Lawrence D David

Anson Jay Call

Robert Anthony Rita

Patrick Anthony Coico

Anthony Mastreani

Stephen Anthony DeLaurentis

Farid Youssif Aoude

David L Edwards

Sung Kwon Kang

Mario John Interrante

Lewis Sigmund Goldmann

William Edward Sablinski

Mukta S Farooq

Suryanarayana Kaja

Gregg B Monjeau

Sarah Huffsmith Knickerbocker

David C Linnell

Renuka S Divakaruni

Scott Ira Langenthal

Hal Mitchell Lasky

Young-Ho Kim

Thomas M Shaw

George Frederick Walker

Jon Alfred Casey

Raschid Jose Bezama

Emanuel Israel Cooper

Sushumna Iruvanti

Raed A Sherif

Glenn Graham Daves

Herbert I Stoller

Harvey Charles Hamel

Hsichang Liu

Peter Richard Duncombe

Mario E Ecker

Karl J Puttlitz, Sr

Jae M Park

James H Covell

Jungihl Kim

Robert R Shaw

Karen P McLaughlin

Mark O Neisser

Kathleen Ann Lidestri

Kim H Ruffing

David H Gabriels

Yee-Ming Ting

Giai V Yen

Edward A Giess

Friedel Muller-Landau

Jon A Van Hise

James M Brownlow, Deceased

Irene S Frantz

John Thomson

Sharon L Tracy

Robert M Troncillito

Peter Alfred Gruber

Krishna Gandhi Sachdev

Charles Hampton Perry

James N Humenik

Robert William Pasco

Daniel George Berger

Brenda Lee Peterson

Srinivasa S N Reddy

Srinivasa N Reddy

Li Ming Wang

Richard A Shelleman

Sara H Knickerbocker

Katharine G Frase

Nancy C Stoffel

Katherine G Frase

Srinivasan N Reddy

A pre-thermal reflown dielectric interposer having a plurality of vias traversing through the interposer which correspond to the I/O pads on a chip and substrate. Cone shaped solder elements reside within the vias, whereby these solder elements are cone shaped prior to thermal reflow to permit a reduced force for allowing some non-planarity for joining the chip to the substrate. The interposer may comprise a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. The interposer may also have an adhesive or adhesive layers disposed on the linear surfaces thereof. The present pre-thermal reflown interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads, as well as preventing over compression of the solder joints by acting as a stand off.

Dielectric interposer for chip to substrate soldering

Interconnection process for module assembly and rework

A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs. The ability of the cone shaped solder interconnects to meet the opposing surface of a chip or substrate at different heights accommodates the camber typically associated with chip and substrate surfaces.

Process for forming cone shaped solder for chip interconnection

A composite electronic and/or optical substrate including polymeric and ceramic material wherein the composite substrate has a dielectric constant less than 4 and a coefficient of thermal expansion of 8 to 14 ppm/&deg;C. at 100&deg; C. The composite substrate may be either ceramic-filled polymeric material or polymer-filled ceramic material.

Polymer and ceramic composite electronic substrates

A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.

Decoupling capacitor method and structure using metal based carrier

The present invention relates generally to a new apparatus and method for introducing thermal paste into semiconductor packages. More particularly, the invention encompasses an apparatus and a method that uses at least one preform of thermal paste for the cooling of at least one chip in a sealed semiconductor package. The thermal paste preform is subcooled, and is transferred onto a module component from a separable transfer sheet, or is placed onto the module component using an attached and/or imbedded mesh. The preform of thermal paste may be of simple or complex shape, and enables cooling of one or more chips in a module.

Thermal paste preforms as a heat transfer media between a chip and a heat sink and method thereof

A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

Copper-based paste containing copper aluminate for microstructural and shrinkage control of copper-filled vias

The present invention relates generally to an electrical interconnection package and a method thereof. More particularly, the invention encompasses an invention that increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. This invention structurally couples at least one module to an organic interposer using a high modulus underfill material. The organic interposer is then joined to a organic board using standard joining processes. The inventive module can then be removed from the organic board at any time by moving the organic interposer using standard rework techniques.

Electrical interconnection package and method thereof

A socketable ball grid array structure is disclosed which comprises mechanically rigid (compared to solder alloys) balls coated with noble contact metals joined to the chip carrier terminals by means of a novel electrically conducting adhesive. Because of the nature of the filler that includes conducting particles with a fusible coating and the appropriate selection of the polymer resin used in the adhesive, the balls are attached to the module in a compliant and resilient manner while leaving the majority of the bottom surface of the balls pristine. The array of balls can therefore be plugged into mating sockets in a printed circuit board forming a demountable contact. This facilitates easy removal of the socketable BGA from a board for repair or upgrade purposes as well as allows ease of plugging and unplugging of these BGA's into test and burn-in boards.

Structure, materials, and methods for socketable ball grid

A new interconnection scheme of a ball grid array (BGA) module is disclosed where a solder ball is connected to the BGA module by use of an electrically conducting adhesive The electrically conducting adhesive can be a mixture comprising a polymer resin, no-clean solder flux, a plurality of electrically conducting particles with an electrically conducting fusible coating and others. The solder balls in a BGA module can also be connected to a printed circuit board by use of another electrically conductive adhesive which can be joined at a lower temperature than the first joining to the BGA module. Additionally, an electrically conducting adhesive can be formed into electrically conducting adhesive bumps which interconnect an integrated circuit device to the BGA module.

Structure, materials, and applications of ball grid array interconnections

This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.

Method for enhancing fatigue life of ball grid arrays

The present invention relates generally to high density pluggable connector array and process thereof. More particularly, the invention encompasses a structure comprising high density pluggable connector arrays. A process for making such types of high density pluggable connector arrays is also disclosed.

High density pluggable connector array and process thereof

An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below &plus;230&deg; C. and detach from the electronic module during subsequent reflows. A Pb&mdash;Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Interconnection structure and process module assembly and rework

An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

Method for a thin film multilayer capacitor

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Hopewell Junction, NY, United States of America

Shaji Farooq