International Business Machines Corporation

Globalfoundries Inc.

Other

Shahab Siddiqui

Michael Patrick Chudzik

Unoh Kwon

Siddarth A Krishnan

Min Dai

Carl John Radens

Kevin Shawn Petrarca

Charlotte DeWan Adams

Barry P Linder

Ravikumar Ramachandran

Jinping Liu

Rishikesh Krishnan

Joseph Francis Shepard, Jr

Daniel James Dechene

Kai Zhao

Karl W Barth

Sean M Polvino

Devendra K Sadana

Takashi Ando

Keith E Fogel

Vijay Narayanan

Dechao Guo

Joel Pereira De Souza

Steven John Koester

Edward William Kiewra

Darryl D Restaino

Christopher Carr Parks

Balaji Kannan

Maryjane Brodsky

Wing L Lai

Beth Baumert

Ruilong Xie

Chen Zhang

Daniel C Edelstein

Shom Ponoth

Dominic Joseph Schepis

Matthew Earl Colburn

Shreesh Narasimha

John Anthony Fitzsimmons

Koji Watanabe

Christos Dimitrios Dimitrakopoulos

Vincent James McGahay

Erdem Kaltalioglu

Jeffrey Curtis Hedrick

Christopher Joseph Waskiewicz

Kaushik Arun Kumar

Christy Sensenich Tyberg

Ricardo Alves Donaton

Dmitriy Shneyder

Murshed Mahmud Chowdhury

Ramona Kei

Delores A Bennett

Spyridon Galis

Chih-Chien Liu

Ruqiang Bao

Ping-Chuan Wang

Hsueh-Chung Chen

Haiting Wang

Martin Michael Frank

Ronald G Filippi

Satyanarayana Venkata Nitta

Shesh Mani Pandey

Yiheng Xu

Jay William Strane

Tong-Yu Chen

Scott Beasor

Yanfeng Wang

Lijuan Zhang

Sameer Hemchand Jain

Gwo-Shii Yang

Paul Andrew Ronsheim

Suresh Uppal

Wei Zhao

Chiung-Sheng Hsiung

Yue Zhong

Shahrukh Akbar Khan

Elnatan Mataev

Abu Naser M Zainuddin

Luigi Pantisano

John Fritche

Abu Naser Zainuddin

Satyanarayana V Nittta

Chih-Chih Liu

Ting-Hsiang Hung

Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance

A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

Gate stacks with multiple high-κ dielectric layers

A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

Gate oxide for nanosheet transistor devices

Embodiments of the invention are directed to a semiconductor device that includes a channel fin; a trench adjacent to an upper region of the channel fin; and an oxygen-blocking layer within the trench. The oxygen-blocking layer includes an oxygen gettering material configured to remove oxygen from an environment to which the oxygen-blocking layer is exposed.

Vertical transistor having an oxygen-blocking layer

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a top spacer trench adjacent to an upper region of the channel fin. An oxygen-blocking layer is deposited within the top spacer trench and over the upper region of the channel fin. A top spacer is formed within the top spacer trench and over a portion of the oxygen-blocking layer that is within the top spacer trench. The oxygen-blocking layer includes an oxygen gettering material.

Vertical transistor having an oxygen-blocking top spacer

At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.

Methods, apparatus and system for forming a FinFET device comprising a first portion capable of operating at a first voltage and a second portion capable of operating at a second voltage

A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.

Methods and structure to form high K metal gate stack with single work-function metal

A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.

Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same

Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOlayer over the second silicon oxy-nitride layer and ILs.

Thermal oxide equivalent low temperature ALD oxide for dual purpose gate oxide and method for producing the same

One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

Integrated circuit structure having thin gate dielectric device and thick gate dielectric device

A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.

Higher 'K' gate dielectric cap for replacement metal gate (RMG) FINFET devices

A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

TSV deep trench capacitor and anti-fuse structure

A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

Fabrication of higher-K dielectrics

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White Plains, NY, United States of America

Shahab Siddiqui