Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Seungyoon Lee

Jeongjin Lee

Chan Soo Hwang

Doogyu Lee

Suntae Hwang

Minseok Kang

Dongjoo You

Hyunsun Yoo

Sangwook Park

Minho Choi

Sungeun Lee

Jungmin Ha

Sunghyun Hwang

Heonmin Lee

Kwangsun Ji

Sehwon Ahn

Youngjoo Eo

Woo-yong Jung

Hongcheol Lee

Chorong Park

Chan Young Hwang

Minhyuck Choi

Jinwon Chung

Joongyeol Ko

Hyunja Shim

Jinsun Kim

Jaebeom Cho

Hyunjay Kang

An overlay correcting method capable of optimizing correction of an overlay within a scanner correction limit of a scanner of a scanner system, and a photolithography method, a semiconductor device manufacturing method and the scanner system which are based on the overlay correcting method are provided. The overlay correcting method includes collecting overlay data by measuring an overlay of a pattern; calculating correction parameters of the overlay by performing regularized regression using the overlay data, the regularized regression being based on a correction limit of the scanner such that the correction parameters fall within the correction limit of the scanner; and providing the correction parameters to the scanner.

Overlay correcting method, and photolithography method, semiconductor device manufacturing method and scanner system based on the overlay correcting method

Disclosed are an overlay correction method, a method of evaluating an overlay correction operation, and a method of fabricating a semiconductor device using the overlay correction method. The overlay correction method may include measuring an overlay between center lines of lower and upper patterns on a wafer, fitting each of components of the overlay with a polynomial function to obtain first fitting quantities, and summing the first fitting quantities to construct a correction model. The components of the overlay may include overlay components, which are respectively measured in two different directions parallel to a top surface of a reticle. The highest order of the polynomial function may be determined as an order, which minimizes a difference between the polynomial function and each of the components of the overlay or corresponds to an inflection point in a graph of the difference with respect to the highest order of the polynomial function.

Overlay correction method, method of evaluating overlay correction operation, and method of fabricating semiconductor device using the overlay correction method

A method of manufacturing a semiconductor device is provided. The method includes transferring an internal shot and an external shot by performing a patterning process on a first wafer, analyzing an overlay of the first wafer, and performing a lithography process on a second wafer, based on the analyzing of the overlay of the first wafer, wherein the analyzing of the overlay of the first wafer includes providing, to the first region, first augmented overlays generated based on an orthogonal coordinate system using first and second directions perpendicular to each other as an axis, and providing, to the second region, second augmented overlays that are overlays in a radial direction from the center of the first wafer.

Method of manufacturing a semiconductor device

An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

Overlay correction method and semiconductor fabrication method including the same

Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

EUV exposure apparatus, and overlay correction method and semiconductor device fabricating method using the same

An electronic device comprises a middle housing; a frame including a first frame and a second frame, each of which have one end respectively coupled to both the left and right sides of the middle housing; a body housing coupled to the frame such that electronic parts are loaded therein; and a frame adjusting part for adjusting an angle between the first frame and the second frame or an arrangement thereof. The electronic device includes the frame adjusting part capable of changing the angle of a band hung around the neck of changing the angle of a band hung around the neck of a user, and thus is conveniently removed and can be stably fixed when worn.

Electronic device

A method of correcting an overlay includes: forming a first pattern on a first substrate; forming a second pattern on the first pattern; obtaining a first overlay error profile of the second pattern and obtaining a first overlay correction profile from the first overlay error profile; forming a third pattern on the second pattern; obtaining a second overlay error profile of the third pattern and obtaining a second overlay correction profile from the second overlay error profile; and forming the second pattern on a second substrate, wherein the forming of the second pattern on the second substrate includes: determining whether the second overlay correction profile has a non-correctable model parameter; and when the second overlay correction profile has the non-correctable model, obtaining a preliminary correction profile to correct a position of the second pattern to be formed on the second substrate.

Overlay-correction method and a control system using the same

Provided is a solar cell including: a semiconductor substrate; a conductive area disposed on one surface of the semiconductor substrate; a first electrode line disposed on the conductive area and extending in a first direction; and a second electrode line disposed on the conductive area and extending in a second direction different from the first direction, wherein the first electrode line includes first particles having a spherical shape and a first average diameter, and the second electrode line includes the first particles and second particles, the second particles having a non-spherical shape and a second average diameter.

Solar cell

A method for measuring overlay includes receiving a first image of a first overlay mark captured using light having a first wavelength. The method includes receiving a second image of a second overlay mark captured using light having a second wavelength different from the first wavelength. The method includes measuring a displacement between a central portion of the first image and a central portion of the second image, wherein the first and second overlay marks are disposed on different levels.

Methods for measuring overlays

A silicon thin film solar cell is discussed. The silicon thin film solar cell includes a substrate on which light is incident, a first electrode positioned on the substrate at a surface opposite a surface of the substrate on which the solar light is incident, a second electrode positioned on the first electrode, at least one photoelectric conversion unit positioned between the first electrode and the second electrode, and a back reflection layer positioned between the at least one photoelectric conversion unit and the second electrode. The back reflection layer includes a first reflection layer formed of a material having an absorption coefficient equal to or less than 400 cmwith respect to light having a wavelength equal to or greater than 700 nm.

Silicon thin film solar cell

A thin film solar cell module includes a substrate, at least one first cell positioned in a central area of the substrate, and at least one second cell positioned in an edge area of the substrate. Each of the first and second cells includes a first electrode, a second electrode, and at least one photoelectric conversion unit positioned between the first electrode and the second electrode. An amount of germanium contained in the photoelectric conversion unit of the first cell is less than an amount of germanium contained in the photoelectric conversion unit of the second cell positioned on the same level layer as the photoelectric conversion unit of the first cell.

Thin film solar cell module

A solar cell is disclosed. The solar cell includes a substrate, a first electrode on the substrate, a second electrode, and a photoelectric transformation unit between the first electrode and the second electrode. The photoelectric transformation unit includes a first intrinsic (referred to as an i-type) semiconductor layer formed of amorphous silicon doped with at least one of carbon (C) and oxygen (O) as impurities and a second i-type semiconductor layer formed of germanium (Ge)-doped microcrystalline silicon.

Growing community of inventors

Seoul, South Korea

Seungyoon Lee