Sandisk Technologies Inc.

Sandisk Corporation

Seungpil Lee

Man Lung Mui

Hao Nguyen

Yingda Dong

Yan Li

Siu Lung Chan

Jian Feng Chen

Jongmin Park

Gautam Ashok Dusija

Deepak Chandra Sekar

Nima Mokhlesi

Teruhiko Kamei

Fanglin Zhang

Alex Mak

Ken Oowada

Hock C So

Chris Nga Yee Avila

Shahzad Khalid

Alexander Kwok-Tung Mak

Juan Lee

Kwang Ho Kim

Prashanti Govindu

Chi-Ming Wang

Khanh Vinh Nguyen

Yosuke Kato

Toru Ishigaki

Jong Park

Masaaki Higashitani

Johann Alsmeier

Gerrit Jan Hemink

Chris Avila

Alon Marcu

Kwang-Ho Kim

Yacov Duzly

Fumitoshi Ito

Yuval Kenan

Deepanshu Dutta

Sergey Anatolievich Gorobets

Tuan Duc Pham

Steven Theodore Sprouse

Dengtao Zhao

Fumiaki Toyama

Raul Adrian Cernea

Tien-Chien Kuo

Changyuan Chen

Tai-Yuan Tseng

Ali K Al-Shamma

Mrinal Kochar

Cynthia Hsu

Yingchang Chen

Qui V Nguyen

Pao-Ling Koh

Jongsun Sel

Jong Hak Yuh

Sung-En Wang

Tapan Samaddar

Yen-Lung Li

Alexander Chu

Amul Dhirajbhai Desai

Masahide Matsumoto

Yee Lih Koh

Alexander Tsang-Nam Chu

Vamsi Krishna Sakhamuri

Man Lung Lui

A first workpiece includes first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad. A second workpiece includes second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece. The first and second workpieces are bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad. Connectivity detection circuits test electrical connectivity between the third test pad and the fourth test pad.

Connectivity detection for wafer-to-wafer alignment and bonding

A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the resultant voltage level on the sensing node used to determine the result of the sensing operation.

Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory

A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. To reduce noise, a decoupling capacitor is connected to the control gate of the discharge transistor and an auxiliary keeper current is run through the discharge transistor.

Sense amplifier with negative threshold sensing for non-volatile memory

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Techniques for programming of select gates in NAND memory

Apparatuses, systems, and methods are disclosed for accessing non-volatile memory. A bit line is coupled to storage cells for a non-volatile memory element. A sense amplifier is coupled to a bit line. A sense amplifier includes a sense circuit and a bias circuit. A sense circuit senses an electrical property of a bit line for reading data from one or more storage cells, and a bias circuit applies a bias voltage to the bit line for writing data to one or more storage cells. A bias circuit and a sense circuit comprise separate parallel electrical paths within a sense amplifier.

Sense amplifier with program biasing and fast sensing

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp circuit is connected to first and second supply levels, a first level used for setting a program inhibit level on bit lines and a second level used for pre-charging bit lines for sensing operation. Outside of a data latch, the sense amp can employ only NMOS transistors. The arrangement of the circuit also allows for the discharging the bit line at the same time as transfers the sensing result out to other latches.

Compact high speed sense amplifier for non-volatile memory with reduced layout area and power consumption

A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.

High endurance non-volatile storage

An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

Selective word line erase in 3D non-volatile memory

A compact and versatile high speed sense amplifier suitable for use in non-volatile memory circuits is presented. The sense amp includes a latch, which is connected to a data bus, and bit line selection circuitry by which it can selectively be connected to one or more bit lines. The sense amp also includes some intermediate circuitry having a first node connectable to a selected bit line through the bit line selection circuitry and a second node that is connectable to the latch circuit. The sense amp can include switches where the second node can be connected to either the value held in the latch or the inverse of the value held in the latch. The sense amp can also include a switch where an internal node of the sense amp can be connected directly to a voltage supply level.

Compact high speed sense amplifier for non-volatile memory

In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

System for maintaining back gate threshold voltage in three dimensional NAND memory

When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

Adaptive operation of three dimensional memory

Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.

Selection of data for redundancy calculation in three dimensional nonvolatile memory

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San Ramon, CA, United States of America

Seungpil Lee