Globalfoundries Inc.

Globalfoundries U.S. Inc.

Seungman Choi

Wolfgang Sauter

David Brian Stone

Nicholas A Polomoff

Mark William Kuemerle

Cathryn Jeanne Christiansen

Zhuojie Wu

Ronald Gene Filippi, Jr

Eric W Tremble

Anil Kumar

Tian Shen

Yuncheng Song

Patrick Ryan Justison

Kong Boon Yeap

Eric S Parent

Jawahar P Nayak

Linjun Cao

A photonic integrated circuit (PIC) structure includes a substrate, and a cavity defined in the substrate, the cavity including a shoulder at a side of the cavity. A plurality of z-stop supports for an optical device are also included. Each z-stop support of the plurality of z-stop supports is on a support portion of the shoulder. A wire extends over the side of the cavity and between at least two z-stop supports of the plurality of z-stop supports. An optical device is positioned on the plurality of z-stop supports in the cavity and electrically coupled to the wire. Electrical connections between z-stop supports allows larger sized electrical connections to the optical device to mitigate electromigration issues, and increased options for electrical connections.

PIC structure with wire(s) between z-stop supports on side of optical device attach cavity

An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.

Interconnected integrated circuit (IC) chip structure and packaging and method of forming same

An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

Parallel test structure

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Loudonville, NY, United States of America

Seungman Choi