Samsung Electronics Co., Ltd.

Seung-Yong Cha

Jang-Keun Oh

Keung Beum Kim

Hyunjong Moon

Heeseok Lee

Yonghoon Kim

Jin-gon Lee

Jung-gyun Han

Inho Choi

Yong-hoon Kim

Min-ha Kim

Kyung Suk Oh

Ae-Nee Jang

Sun-Won Kang

Hyun-Ju Lee

Yun-Hee Lee

Jang-keun Oh

Hyun-ju Lee

Eunseok Song

Eun-Seok Song

Jae-Choon Kim

Seongho Shin

Ju-Youn Choi

Yoonha Jung

Hyoun-soo Kim

Min-Ha Kim

Ji-chul Kim

Tongsuk Kim

Tai-Hyun Eum

Jung-Gyun Han

Si-Chang Riu

Jin-Gon Lee

A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

System-in-package module

An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.

Electronic device package

An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals. The logic chip processes pixel signals from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip. The memory chip structure includes a memory chip, a molding portion surrounding the memory chip, and at least one through mold via contact vertically passing through the molding portion and connected to at least one of the logic or memory chip. The memory chip stores at least one of a pixel signal processed by the logic chip or a pixel signal from the image sensor chip and receives the power voltage, ground voltage, or signals via the image sensor chip and logic chip.

Image sensor package having multi-level stack structure

A semiconductor package includes a first package and a second package stacked on the first package. The first package includes a redistribution substrate, a first semiconductor chip on the redistribution substrate, a connection substrate provided on the redistribution substrate to surround the first semiconductor chip as viewed in plan, and an inductor structure provided within a first region of the connection substrate and electrically connected to the first semiconductor chip through the redistribution substrate. The second package includes at least one outer terminal electrically connected to the first package. The outer terminal is provided on a second region of the connection substrate, and when viewed in plan, the first region and the second region are spaced apart from each other.

Semiconductor packages

A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

Semiconductor memory device for improving signal integrity issue in center pad type of stacked chip structure

A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Semiconductor packages including thermal blocks

A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.

Semiconductor package

A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns.

Semiconductor device

A suction body for a cleaner is provided that can generate electric energy by itself using air drawn in by the cleaner. A suction body includes an ultraviolet sterilizer that radiates ultraviolet rays toward a surface to be cleaned and sterilizes the surface to be cleaned, a lighting device that emits light, a displaying device that displays a cleaning state, a fan that rotates by drawn-in air, and a generator that converts rotary energy of the fan into electric energy so as to supply the electric energy to the ultraviolet sterilizer, the lighting device, and the displaying device.

Suction body providing electric energy and cleaner having the same

A semiconductor chip including a termination resistance and a semiconductor module including the semiconductor chip. The semiconductor chip comprising a plurality of memory cells, the semiconductor chip including: at least one first center pads disposed on a center region of the semiconductor chip and connected to the plurality of memory cells; at least one first edge pads disposed on an edge region of the semiconductor chip and connected to a first transmission line of a semiconductor module; at least one second edge pads disposed on the edge region of the semiconductor chip and connected to a chipset voltage application unit of the semiconductor module; at least one first redistribution patterns connected between the at least one first center pads and the at least one first edge pads; and at least one second redistribution patterns connected between the at least one first edge pads and the at least one second edge pads, wherein an impedance of the at least one second redistribution patterns is impedance matched to an impedance of the first transmission line.

Semiconductor chip and semiconductor module including the semiconductor chip

Growing community of inventors

Gwangju, South Korea

Seung-Yong Cha