Skhynix Inc.

Seung Yeop Lee

Han Jun Bae

Ju Il Eom

Chang Hwi Lee

Jin Su Park

Jong Hoon Kim

Jin Woo Kim

Hyun Chul Seo

Soon Sung An

Jae Hyeong Hong

Heon Ki Kim

Joo Hyun Kang

Hyun Duck Lee

Young Jo Park

Jung Yeop Lee

Se Min Lee

Hee Jeong Son

Nam Hea Jang

Ji Eun Joo

Young Seok Nam

Ju Hyeong Lee

Ki Ryong Jung

An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

Internal reference voltage generation device

A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface that is connected to the signal redistribution pad and a lower surface that is connected to the substrate; a power sub interconnector with an upper surface that is connected to the power redistribution pad and a lower surface that is connected to the substrate; and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate.

Semiconductor package including stacked semiconductor chips

A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.

A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.

Semiconductor integrated circuit device including an electro-static discharge protection circuit

Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.

Semiconductor device using wires and stacked semiconductor package

A semiconductor integrated circuit device may include a pad, a first voltage protection unit and a second voltage protection unit. The first voltage protection unit may be connected with the pad. The first voltage protection unit may be configured to maintain a turn-off state when a test voltage having a negative level may be applied from the pad. The second voltage protection unit may be connected between the first voltage protection unit and a ground terminal. The second voltage protection unit may be turned-on when an electrostatic voltage having a positive level may be applied from the pad. The second voltage protection unit may include a plurality of gate positive p-channel metal oxide semiconductor (GPPMOS) transistors serially connected with each other.

Semiconductor integrated circuit device including an electrostatic discharge protection circuit

A stack package includes a supporting substrate that supports first and second semiconductor dies. The supporting substrate is disposed on a package substrate and is supported by first and second connection bumps. Redistributed line (RDL) patterns are disposed on the supporting substrate to electrically connect the first semiconductor die to the first and second connection bumps. The second semiconductor dies are connected to the package substrate by bonding wires.

Stack packages including a supporting substrate

A stack package includes a package substrate and a fan-out sub-package mounted on the package substrate using first and second connection bumps. The fan-out sub-package includes a first semiconductor die and redistributed line (RDL) patterns. Second semiconductor dies are stacked on the package substrate to provide a first step structure, and third semiconductor dies are stacked on the second semiconductor dies to provide a second step structure. The second and third semiconductor dies are connected to the package substrate by bonding wires.

Stack packages including a fan-out sub-package

A semiconductor package may include a first chip stack including first chips which are stacked on a package substrate. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate. The semiconductor package may include a third chip disposed on the first and second chip stacks.

Semiconductor packages including stacked chips

A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. The second conductive pattern includes a second sliding contact portion overlapping with the first sliding contact portion and the second conductive pattern includes a second extension portion. The second sliding contact portion is in contact with the first sliding contact portion and is movable on the first sliding contact portion for a sliding motion. The first and second conductive patterns are embedded in the dielectric layer.

Flexible device including sliding interconnection structure

A semiconductor device is provided. The semiconductor device may include a substrate and a through via structure penetrating the substrate. The through via structure may provide a dual path that may include an electrical path and an optical path. Related electronic systems and memory cards are also provided.

Semiconductor devices with optical through via structures, memory cards including the same, and electronic systems including the same

A semiconductor chip includes a semiconductor substrate having one surface, the other surface which faces away from the one surface, and an integrated circuit which is formed on the one surface; and a shielding layershielding layer formed in the semiconductor substrate to correspond to the other surface.

Semiconductor chip and semiconductor package having the same

A multi-chip package includes a lower substrate; at least two semiconductor chips stacked over the lower substrate and each defined with a via hole; an upper substrate coupled to a semiconductor chip positioned uppermost among the semiconductor chips; a light emitting part coupled to the lower substrate corresponding to the via hole; an electrowetting liquid lens coupled to a lower surface of the upper substrate for receiving a signal transferred from the light emitting part through the via hole; a light receiving part coupled to a sidewall of the via hole of each semiconductor chip configured to receive a signal from the electrowetting liquid lens.

Multi-chip package cross-reference to related applications

A semiconductor device includes a semiconductor chip and an inner interconnection structure. The semiconductor chip includes a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals. The inner interconnection structure includes horizontal buried conductive lines and vertical connection lines disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals.

Semiconductor device including inner interconnection structure able to conduct signals or voltages in the semiconductor chip with vertical connection vias and horizontal buried conductive lines

Growing community of inventors

Suwon-si, South Korea

Seung Yeop Lee