Globalfoundries Inc.

Seung Yeon Kim

Wei Hua Tong

Haiting Wang

Huang Liu

Weihua Tong

Jin Ping Liu

Yan Ping Shen

Tien-Ying Luo

Feng Zhou

Haoran Shi

Min-Hwa Chi

Jinping Liu

Haigou Huang

Andy C Wei

Hongliang Shen

Bharat V Krishnan

Changyong Xiao

Akshey Sehgal

Sandeep Gaan

Teck Jung Tang

Bongki Lee

Hsin-Neng Tai

Francis M Tambwe

Jun Lian

Sang Cheol Han

Vidmantas Sargunas

Kyutae Na

Tae Hoon Kim

Ja Hyung Han

Yong Meng Lee

Yiqun Liu

Tae-Hoon Kim

HongLiang Shen

Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Conformal nitridation of one or more fin-type transistor layers

Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a 'buffer zone' or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Shallow trench isolation integration methods and devices formed thereby

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Integrated circuits having finFETs with improved doped channel regions and methods for fabricating same

A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Forming a gate by depositing a thin barrier layer on a titanium nitride cap

A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Methods of forming a FinFET semiconductor device with undoped fins

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Integrated circuits having FinFETs with improved doped channel regions and methods for fabricating same

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same

One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Methods of forming a finfet semiconductor device with undoped fins

A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Integrated circuits having replacement gate structures and methods for fabricating the same

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Andover, MA, United States of America

Seung Yeon Kim