Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Seung Wan Shin

Seung Wook Park

Young Do Kweon

Mi Jin Park

Kyung Seob Oh

Hyung Jin Jeon

Jong In Ryu

Seon Hee Moon

Seung Jin Oh

Ho Jun Jung

A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first semiconductor chip having a first active surface having first connection pads; a first encapsulant encapsulating the first semiconductor chip; a first connection member disposed on the first active surface and including a first redistribution layer electrically connected to the first connection pads; a second semiconductor chip having a second active surface having second connection pads; a second encapsulant covering the first connection member and encapsulating the second semiconductor chip; a second connection member disposed on the second active surface and including a second redistribution layer electrically connected to the second connection pads; and a third via penetrating through the second encapsulant, connecting the first redistribution layer and the second redistribution layer to each other, and including a metal post connected to the first redistribution layer and a via conductor disposed on the metal post and connected to the second redistribution layer.

A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer.

Method for manufacturing interposer

There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities.

Growing community of inventors

Suwon-si, South Korea

Seung Wan Shin