Samsung Electronics Co., Ltd.

Seung-Mok Shin

Jae-Jong Han

Sang-Hoon Lee

Kong-Soo Lee

Kyung-Tae Jang

Jung-Hwan Kim

Ki-Hyun Hwang

Eun-jung Yun

Young-wook Park

Jin-Hong Kim

Mi-Sun Do

Byung-Ki Kim

Myoung-Bum Lee

Hun-Hyeoung Leam

Jong-Ho Bang

Bong-hyun Kim

Woo-Sung Lee

Chang-Won Lee

Soo-Jin Hong

Hyun-Jin Shin

Yong-Woo Hyung

Kyoung-Seok Kim

Man-Sug Kang

Jai-Dong Lee

Tae-Jong Han

Ju-Wan Kim

Won-Seok Yoo

Soo-woong Lee

Yong-Sun Lee

Bon-young Koo

Ji-Youn Seo

Ji-Woon Im

Koong-Hyun Nam

Sung-Eui Kim

Hyun-Yong Go

Gi-Hyun Hwang

Yung-Seob Yu

Jang-Woo Son

In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Vertical memory devices and methods of manufacturing the same

A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.

Vertical non-volatile memory device

A system and method for providing Multicast/Broadcast Service (MBS) service to a mobile terminal in an MBS service provisioning system in a Wide Area Network (WAN) network are provided. An authentication server sends a message for requesting resource reservation, in which a Quality-of-Service (QoS) policy is included, when a registration procedure of the mobile terminal is performed. A base station stores the message sent from the authentication server, forwards the message to the mobile terminal, and sets up a channel to the mobile terminal upon receiving from the mobile terminal a request for channel setup based on the QoS policy.

Method for providing MBS service in a WAN network, and system thereof

Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Methods of manufacturing a semiconductor device

According to example embodiments of the present invention, there are provided an electrical node of a transistor and a method of forming the same, which may reduce or minimize current leakage between the electrical node and a semiconductor substrate when a buried contact hole exposing at least the side of an active region is arranged on the semiconductor substrate. Two gate patterns may be formed on the active region of the semiconductor substrate. Conductive layer patterns may be formed in the gate patterns and in the semiconductor substrate between the gate patterns. A buried interlayer insulating layer may be formed on the semiconductor substrate to cover the gate patterns. A buried contact hole which passes through the buried interlayer insulating layer and exposes the conductive layer pattern of the semiconductor substrate may be formed. The buried contact hole may be formed to expose at least the side of the active region. An impurity region may be formed in the semiconductor substrate below the buried contact hole. A contact hole spacer covering the sidewall of the buried contact hole may be formed. A buried conductive layer which covers the contact hole spacer and fills the buried contact hole may be formed.

Electrical node of transistor and method of forming the same

In accordance with a method of trench isolation, a first oxide layer is formed on a semiconductor substrate. A first conductive layer and a nitride layer are successively formed on the first oxide layer. The nitride layer, the first conductive layer and the first oxide layer are etched to form a nitride layer pattern, a first conductive layer pattern and an oxide layer pattern. A portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench in the substrate. The trench is cured under dinitrogen monoxide (NO) or nitrogen monoxide(NO) atmosphere. A second oxide layer is formed in the trench through an in-situ process.

Method of trench isolation and method for manufacturing a non-volatile memory device using the same

In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.

Method of forming a gate electrode, method of manufacturing a semiconductor device having the gate electrode, and method of oxidizing a substrate

A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

Method of manufacturing a semiconductor device including alignment mark

A method for forming a self-aligned contact in a semiconductor device which can reduce process failures and a method for manufacturing a semiconductor device that includes the self-aligned contact are provided. A self-aligned contact hole is formed in an interlayer dielectric film to expose a portion of the substrate between conductive structures formed thereon. A buffer layer is formed on a sidewall of the self-aligned contact hole, on the bottom of the self-aligned contact hole, and on the interlayer dielectric film such that the thickness of the buffer layer at an upper portion of the self-aligned contact hole is greater than the thickness of the buffer layer at the bottom of the self-aligned contact hole. After removing the portion of the buffer layer on the bottom of the self-aligned contact hole, a contact is formed in the self-aligned contact hole to make contact with the substrate.

Method for forming a self-aligned contact of a semiconductor device and method for manufacturing a semiconductor device using the same

Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.

Methods of forming trench isolation regions having stress-reducing nitride layers therein

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Suwon-si, South Korea

Seung-Mok Shin