Samsung Electronics Co., Ltd.

Seung-Bum Ko

Byung-Hoon Jeong

Byung-Chul Kim

Byung-sik Moon

Woo-seop Jeong

Byung-Hyun Lee

Beob-Rae Cho

Han-Gyun Jung

Jeong-suk Yang

A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.

Semiconductor memory device capable of preventing damage to a bitline during a data masking operation

Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

CAS latency circuit and semiconductor memory device including the same

A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.

Circuit and method for controlling write recovery time in semiconductor memory device

Provided are a synchronous semiconductor device having constant data output time regardless of a bit organization, and a method of adjusting data output time. The synchronous semiconductor device includes an internal clock generator for receiving an external clock and generating an internal clock, a clock controller for adjusting the phase of the internal clock and generating a data output clock in response to bit organization information, and a data output buffer for outputting data read from a memory cell to the outside in response to the data output clock. Thus, it is possible to prevent vertical vibration in a disc loaded in a disc driver regardless of wobble of the disc.

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Hwaseong-si, South Korea

Seung-Bum Ko