Intermolecular, Inc.

Northrop Grumman Systems Corporation

Elpida Memory, Inc.

First Solar, Inc.

Sergey V Barabash

Dipankar Pramanik

Tony P Chiang

Karl Anthony Littau

Xiangxin Rui

Mankoo Lee

Xuena Zhang

Charlene Chen

Andrew Steinbach

Vijay Kris Narasimhan

Chris Kirby

Stephen Weeks

Yun Yu Wang

Zhi-Wen Sun

Federico Nardi

Amir Bayati

Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400&#xb0; C. or 450&#xb0; C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400&#xb0; C. and, in some embodiments, glass transition temperatures of greater than 400&#xb0; C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

Current compliance layers and memory arrays comprising thereof

A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.

All around electrode for novel 3D RRAM applications

Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Hydrogenated amorphous silicon dielectric for superconducting devices

Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption.

Superconducting circuits with reduced microwave absorption

Embodiments provided herein describe methods for forming cadmium-manganese-telluride (CMT), such as for use in photovoltaic devices. A substrate including a material with a zinc blend crystalline structure is provided. CMT is formed above the substrate. During the formation of the CMT, cation-rich processing conditions are maintained. The resulting CMT may be more readily provided with p-type dopants when compared to conventionally-formed CMT.

Zinc blende cadmium&#x2014;manganese&#x2014;telluride with reduced hole compensation effects and methods for forming the same

A YBCO-based conductive material can be used as an electrode, which can contact a dielectric such as a high k dielectric. Alternatively, a material with a narrow conduction band can be used as an electrode, which can contact a dielectric such as a high k dielectric. By aligning the dielectric with the band gap of the YBCO-based electrode or with the band gap of the narrow-band conductive material electrode, e.g., the conduction band minimum of the dielectric falls into one of the band gaps of the YBCO-based or narrow-band conductive material, thermionic leakage through the dielectric can be reduced, since the excited electrons or holes in the electrode would need higher thermal excitation energy to overcome the band gap before passing through the dielectric layer.

Electrode for low-leakage devices

Provided are method for determining switching conditions for production memory cells based on dopant flux during set and reset operations. One group of test memory cells, which are representative of the production memory cells, is subjected to a prolonged application of a set voltage, while another group is subjected to a prolonged application of a reset voltage. Different durations may be used for different cells in each group. A dopant concentration profile of a test component in each cell is determined for both groups. One cell from each group may be identified such that the changes in the dopant concentration profiles in these two identified cells are complementary. The profile complementarity indicates that these two identified cells had a similar dopant flux during voltage applications. Durations of set and reset voltage applications for these two cells may be used to determine switching conditions for production memory cells.

Switching conditions for resistive random access memory cells

Provided are capacitor stacks for use in integrated circuits and methods of fabricating these stacks. A capacitor stack includes a dielectric layer and one or two inner electrode layers, such as a positive inner electrode layer and a negative inner electrode layer. The inner electrode layers directly interface the dielectric layer. The stack may also include outer electrode layers. The inner electrode layers are either chemically stable or weakly chemically unstable, while in contact with the dielectric layer based on the respective phase diagrams. Furthermore, the electron affinity of the positive inner electrode layer may be less than the electron affinity of the dielectric layer. The sum of the electron affinity and bandgap of the negative inner electrode layer may be less than that of the dielectric layer. In some embodiments, inner electrode layers are formed from heavily doped semiconducting materials, such as gallium arsenide or gallium aluminum arsenide.

Capacitors including inner and outer electrodes

Anisotropic materials, such as rutile TiO, can exhibit dielectric constant of 170 along the tetragonal axis of (001) direction, and dielectric constant of 86 along directions perpendicular to the tetragonal axis. Layer of anisotropic material nanorods, such as TiOnanorods, can form a seed layer to grow a dielectric layer that can exhibit the higher dielectric constant value in a direction parallel to the substrate surface. The anisotropic layer can then be patterned to expose a surface normal to the high dielectric constant direction. A conductive material can be formed in contact with the exposed surface to create an electrode/dielectric stack along the direction of high dielectric constant.

Deposition of rutile films with very high dielectric constant

Provided are resistive switching memory cells having selectors and methods of fabricating such cells. A selector may be disposed between an electrode and resistive switching layer. The selector is configured to undergo an electrical breakdown when a voltage applied to the selector exceeds a selected threshold. The selector is formed from amorphous silicon doped with fluorine. The concentration of fluorine may be between about 0.01% atomic and 3% atomic, such as about 1% atomic. Amorphous silicon has a larger band gap than, for example, crystalline silicon and, therefore, has a lower leakage. Dangling bond and weak bond states appearing in the mid-gap position of amorphous silicon are eliminated by adding fluorine. Fluorine binds to and passivates defects. In some embodiments, a fluorine reservoir is positioned in a low current density region of the memory cell to counter diffusion of fluorine from the selector into other components.

Amorphous silicon doped with fluorine for selectors of resistive random access memory cells

A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.

Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate

Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.

Method of depositing films with narrow-band conductive properties

Steering elements suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the steering element can include a first electrode, a second electrode, and a graded dielectric layer sandwiched between the two electrodes. The graded dielectric layer can include a varied composition from the first electrode to the second electrode. Graded energy level at the top and/or at the bottom of the band gap, which can be a result of the graded dielectric layer composition, and/or the work function of the electrodes can be configured to suppress tunneling and thermionic current in an off-state of the steering element and/or to maximize a ratio of the tunneling and thermionic currents in an on-state and in an off-state of the steering element.

Barrier design for steering elements

An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Growing community of inventors

San Jose, CA, United States of America

Sergey V Barabash