Tru-si Technologies, Inc.

Adeia Semiconductor Bonding Technologies Inc.

Allvia, Inc.

Invensas LLC

Sergey Savastiouk

Valentin Kosenko

Oleg Siniaguine

Sam Kao

Patrick B Halahan

James J Roman

Patrick A Halahan

Alex Berger

Cyprian Emeka Uzoh

Pezhman Monadgemi

Bosco Lan

Edward Lee McBain

Igor Bagriy

Edward Lee Bcbain

Patrick Halahan

Edward Lee Mcbain

A through via () contains a conductor () passing through a substrate () for connection to an integrated circuit element. The through via consists of two segments () formed from respective different sides () of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer () into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.

Substrates with through vias with conductive features for connection to integrated circuit elements, and methods for forming through vias in substrates

A through via contains a conductor () passing through a substrate (). The substrate can be SOI or some other substrate containing two semiconductor layers () on opposite sides of an insulating layer (B). The through via includes two constituent vias () formed from respective different sides of the substrate by processes stopping on the insulating layer (B). Due to the insulating layer acting as a stop layer, high control over the constituent vias' depths is achieved. Each constituent via is shorter than the through via, so via formation is facilitated. The conductor is formed by separate depositions of conductive material into the constituent vias from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the through-via depth, so the deposition is facilitated. Other embodiments are also provided.

Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor

To fabricate an interposer for interfacing waveguides (e.g. optical fiber cables) to transducers, a cavity (410) is formed in a top surface of a substrate. A first layer (520) is formed over the cavity's bottom surface, with one or more gaps in the first layer's top surface. A second layer (3410) is formed in the one or more gaps. The second layer overlaps the first layer. At least part of the first layer is removed to form channels separated from each other by portions of the second layer that are located in the one or more gaps; at least part of the first layer is removed from under the second layer. The second layer portions in the one or more gaps provide one or more spacers in the cavity; these one or more spacers at least partially cover the channels. Waveguides can be placed into the channels.

Structures formed using monocrystalline silicon and/or other materials for optical and other applications

Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor layers

A portion of a conductive layer () provides a capacitor electrode (). Dielectric trenches () are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric () can be formed by anodizing tantalum while a nickel layer () protects an underlying copper () from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer () is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques

An optical interposer includes grooves () for optical fiber cables () coupled to a transducer (). The grooves are formed by etching a cavity () in a substrate (), filling the cavity with some layer (), then etching the layer to form the grooves. The cavity has outwardly sloped sidewalls on which mirrors () are later formed. The groove etch is selective not to damage the sidewalls. The groove depth is uniform due to high etch selectivity of the layer, and also because of good control over the cavity etch due to the low aspect ratio of the cavity. Electrical circuitry for connection to the transducer is fabricated after the cavity filling but before the groove etch. The cavity filling leaves the wafer planar, facilitating fabrication of the electrical circuitry. Grooves can be provided on top and bottom of the interposer. Other features are also provided.

Optical interposer

A through hole () is formed in a wafer () comprising a semiconductor substrate (). A seed layer () is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor () is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric () is formed in an opening in a semiconductor substrate () by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed () is formed on the bottom by electroless plating. A conductor () is electroplated on the seed. In another embodiment, a dielectric () is formed in the opening to cover the entire surface of the opening. A non-conformal layer () is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric () is etched off the bottom with the non-conformal layer () as a mask. A seed () is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby

Vias (B) are formed in a surface of a substrate. At least portions of contact pads () are located in the vias. Contact pads () of an integrated circuit structure are inserted into the vias and attached to the contact pads () of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad () in the substrate but also a surrounding region. Solder () wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (), with the top layer () being more solder wettable than the bottom layer () and the top layer covering only a portion of the bottom layer.

Attachment of integrated circuit structures and other substrates to substrates with vias

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San Jose, CA, United States of America

Sergey Savastiouk