International Business Machines Corporation

Texas Instruments Corporation

Tokyo Electron Limited

National University of Singapore

Interuniversitair Microelektronica Centrum (imec)

Imec Vzw

Serge Biesemans

Terence B Hook

James Albert Slinkman

Byeongju Park

Julien Ryckaert

Dim-Lee Kwong

Eric Adler

Jorge Adrian Kittl

Naoto Horiguchi

Judith H McCullen

Zsolt Tokei

Karanam Balasubramanyam

HongYu Yu

Kathleen Nafus

Micah S Galland

Li Mingfu

Chen JingDe

Eric S Phipps

Bilal Chehab

Techniques herein include methods for selectively modifying chemical properties of organosilicates including periodic mesoporous organosilicates (PMOs) in situ for use in fabrication of semiconductor devices. With techniques herein, such materials are manipulated in their chemical properties after deposition and can accordingly be used as sacrificial patterning films and/or as patterning enabling materials. Using selective treatments such as annealing, curing, plasma exposure, and silylation, chemical properties such as etch resistance and hydrophobicity can be changed to enable a given patterning operation. A given film can be etch resistant for one patterning operation, and then changed to be etch removable for a subsequent patterning operation.

Methods and system of using organosilicates as patterning films

Low work function metals for use as gate electrode in nMOS devices are provided. The low work function metals include alloys of lanthanide(s), metal and semiconductor. In particular, an alloy of nickel-ytterbium (NiYb) is used to fully silicide (FUSI) a silicon gate. The resulting nickel-ytterbium-silicon gate electrode has a work function of about 4.22 eV.

Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET

A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Device modeling for proximity effects

Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.

Method for forming an electronic device

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Leuven, Belgium

Serge Biesemans