Intel Corporation

Serafin E Garcia

Zohar Bogin

David J Harriman

Russell W Dyer

Jasmin Ajanovic

Jeffrey L Rabe

Romesh B Trivedi

Srinivasan T Rajappa

Abdul H Pasha

Rajagopal Subramanian

Steven John Clohset

Mikal Hunsaker

Steve John Clohset

Alberto J Martinez

Satish Acharya

Jackie Wensel

An approach to selecting either an actual stepping revision ID value or a compatible revision ID value to be readable by a processor through a revision ID register.

Method and apparatus for identifying hardware compatibility and enabling stable software images

A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.

Managing bus transaction dependencies

A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

Reordering of burst data transfers across a host bridge

A method and apparatus for delivering APIC interrupts to a processor, and between processors, as FSB transactions. Interrupts and hardware signals, generated by a PCI device, are converted into an upstream memory write interrupt and further converted into an FSB interrupt transaction, received by a processor. Interrupts marked as lowest priority re-directable are redirected based on task priority information. Support for XTPR transactions to update XTPR registers is provided. Preferred ordering of XTPR update transactions and interrupts to be redirected is provided.

Method and apparatus for processing interrupts of a bus

A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Device for spatially and temporally reordering for data between a processor, memory and peripherals

A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.

A technique to reduce accumulated latencies in bus transmission time when a bus inversion scheme is employed. The bus inversion scheme inverts all the data bits whenever more than one-half of the data bits are active, so that the bus never has more that one-half of the bits active during a data transfer. This minimizes the number of driver circuits that are actively driving the bus at any given time. Since it takes a certain amount to time to determine if more than one-half of the bits are active, this process can add to overall latency, or data transfer time on the bus. By placing the bus inversion function in parallel with another function that also contributes to bus latency, such as error correction code (ECC) calculation, only the more time-consuming of the two functions will increase bus latency.

Inserting bus inversion scheme in bus path without increased access latency

A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address formatted in accordance with a peripheral component interconnect (PCI) specification. The configuration access request packet is received from the hub interface by a second hub agent.

Peripheral component interconnect (PCI) configuration emulation for hub interface

An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed. If, however, the timeout counter expires before the posted write buffer becomes available, the memory controller issues a retry response to the processor, indicating to the processor that the first postable write transaction request must be reissued at a later time.

Method and apparatus for improving processor to graphics device throughput

According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order to detect the presence of a second hub agent upon initiation of the computer system. In a further embodiment, the first hub agent comprises a presence detect module and control logic coupled to the presence detect module. The control logic responds to a central processing unit (CPU) poll request if the second hub agent is detected and does not respond to the CPU if the first device is not detected.

Growing community of inventors

Folsom, CA, United States of America

Serafin E Garcia