Samsung Electronics Co., Ltd.

Seong-Geon Park

Sang-Bom Kang

Gil-heyun Choi

You-Kyoung Lee

Kyung-In Choi

Sang-Woo Lee

Jong-Myeong Lee

Yu-Gyun Shin

Hideki Horii

Dong-Ho Ahn

Hye-Lan Lee

Taek-Soo Jeon

Jung-Moo Lee

Min-kyu Yang

Hag-ju Cho

Hyun-Su Ju

Eun-Mi Kim

Byung-Hee Kim

Hong-bae Park

Beom-jun Jin

Hag-Ju Cho

Dong-Jun Seong

Seol Young Choi

A variable resistance memory device includes first conductive lines positioned above a substrate. Each of the first conductive lines extends in a first direction and a second direction. Second conductive lines extend in the first direction and the second direction. The second conductive lines are positioned above the first conductive lines. A memory is positioned between the first and second conductive lines. The memory unit overlaps the first and second conductive lines in a third direction. The memory unit includes a first electrode, a variable resistance pattern positioned on the first electrode, and a second electrode positioned on the variable resistance pattern. A selection pattern is positioned on each memory unit. A third electrode is positioned above the selection pattern. The third electrode is in direct contact with a lower surface of each of the second conductive lines.

Variable resistance memory device and method of manufacturing the same

A variable resistance memory device may include: a first electrode layer; a selection device layer on the first electrode layer, the selection device layer including a chalcogenide switching material consisting essentially of germanium (Ge), selenium (Se), and antimony (Sb), wherein a content of the Ge is less than a content of the Se based on an atomic weight; a second electrode layer on the selection device layer; a variable resistance layer on the second electrode layer, the variable resistance layer including a chalcogenide material; and a third electrode layer on the variable resistance layer.

According to example embodiments, a nonvolatile memory cell includes a first electrode and a second electrode, a resistance change film between the first electrode and the second electrode, and a first barrier film contacting the second electrode. The resist change film contains oxygen ions and contacts the first electrode. The first barrier film is configured to reduce (and/or block) the outflow of the oxygen ions from the resistance change film.

Nonvolatile memory cell and nonvolatile memory device including the same

Nonvolatile stacked memory structure with a resistance change film between a vertical electrode and horizontal electrodes

A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.

Methods of fabricating semiconductor devices having transistors with different gate structures

In a method for forming a field effect transistor, a metal nitride layer is formed on a gate electrode insulating layer. Tantalum amine derivatives represented by the chemical formula Ta(NR)(NRR), in which R, Rand Rrepresent H or a C-Calkyl group, may be used to form the metal nitride layer. Nitrogen may then be implanted into the metal nitride layer to increase the nitrogen content of the layer.

Methods of producing integrated circuit devices utilizing tantalum amine derivatives

Semiconductor devices having transistors with different gate structures and methods of fabricating the same

In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR)(NRR)in which R, Rand Rrepresent H or C-Calkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

Method for forming a wiring of a semiconductor device, method for forming a metal layer of a semiconductor device and apparatus for performing the same

A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed

In a method for forming a wiring of a semiconductor device using an atomic layer deposition, an insulating interlayer is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR)(NRR)in which R, Rand Rrepresent H or C&#x2013;Calkyl group are introduced onto the insulating interlayer. A portion of the tantalum amine derivatives is chemisorbed on the insulating interlayer. The rest of tantalum amine derivatives non-chemisorbed on the insulating interlayer is removed from the insulating interlayer. A reacting gas is introduced onto the insulating interlayer. A ligand in the tantalum amine derivatives chemisorbed on the insulating interlayer is removed from the tantalum amine derivatives by a chemical reaction between the reacting gas and the ligand to form a solid material including tantalum nitride. The solid material is accumulated on the insulating interlayer through repeating the above processes to form a wiring.

Atomic layers can be formed by introducing a tantalum amine derivative reactant onto a substrate, wherein the tantalum amine derivative has a formula: Ta(NR)(NRR), wherein R, Rand Rare each independently H or a C&#x2013;Calkyl functional group, chemisorbing a portion of the reactant on the substrate, removing non-chemisorbed reactant from the substrate and introducing a reacting gas onto the substrate to form a solid material on the substrate. Thin films comprising tantalum nitride (TaN) are also provided.

Methods for forming atomic layers and thin films including tantalum nitride and devices including the same

In a method for forming a gate electrode, a dielectric layer having a high dielectric constant is formed on a substrate. Tantalum amine derivatives represented by a chemical formula Ta(NR)(NRR)in which R, Rand Rrepresent H or C&#x2013;Calkyl group are introduced onto the dielectric layer to form a tantalum nitride layer. A capacitor metal layer or a gate metal layer is formed on the tantalum nitride layer. The capacitor metal layer or the gate metal layer and the tantalum nitride layer are patterned to form a capacitor electrode or a gate electrode. The tantalum amine derivatives are used in forming a dual gate electrode.

A semiconductor device has at least two different gate electrodes. The two different gate electrodes include a first gate electrode on a first gate insulation layer. The first gate electrode includes a first metal-containing conductive pattern on the first gate insulation layer and a second metal-containing conductive pattern. A second gate electrode is provided on a second gate insulation layer and includes a third metal-containing conductive material on the second gate insulation layer. The first metal-containing conductive pattern and the third metal-containing conductive pattern have different work functions from each other. A surface of the second metal-containing conductive pattern and a surface of the third metal-containing conductive pattern are substantially planar. Methods of fabrication such semiconductor devices are also provided.

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Gyeonggi-do, South Korea

Seong-Geon Park