Samsung Electronics Co., Ltd.

Seokhyun Lee

Kyoung Lim Suk

Jaegwon Jang

Jongyoun Kim

Dongkyu Kim

Yeonho Jang

Minjung Kim

Gwangjae Jeon

Jungho Park

Hyeonjeong Hwang

Jin-Woo Park

Ae-Nee Jang

SeokWon Lee

Minjun Bae

Kyounglim Suk

Youn Ji Min

Jongho Lee

Dahye Kim

Kyung Suk Oh

Yun-Rae Cho

Seung-Kwan Ryu

Keung Beum Kim

Taesung Park

Chul-Yong Jang

Sundae Kim

Namgyu Baek

Hyeonseok Lee

Jung-Ho Park

Doohwan Lee

Daeho Lee

MinJung Kim

Taewon Yoo

Hogeon Song

Bangweon Lee

Seokkyu Choi

JeongHo Lee

Inhyung Song

Yaejung Yoon

Inwon O

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a first molding layer on the package substrate and surrounding the first semiconductor chip, a redistribution layer on the first molding layer, a first through via that vertically penetrates the first molding layer and connects the package substrate to the redistribution layer, a second semiconductor chip mounted on the redistribution layer, a second molding layer on the redistribution layer and surrounding the second semiconductor chip, and a second through via that vertically penetrates the second molding layer and is connected to the redistribution layer. A first width of the first through via is less than a second width of the second through via. The second through via is electrically floated from a signal circuit of the second semiconductor chip.

Semiconductor package

A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.

Semiconductor package and method of manufacturing the same

A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.

A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.

Semiconductor package including redistribution substrate and method of manufacturing the same

A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.

Semiconductor package including redistribution substrate

A semiconductor package includes a redistribution substrate including a first surface and a second surface that are opposite to each other, an antenna substrate on the first surface and including a first insulating portion and antenna patterns on a top surface of the first insulating portion, and a first semiconductor chip on the second surface. The redistribution substrate includes a second insulating portion, and a redistribution pattern in the second insulating portion. The redistribution pattern includes an interconnection portion extending parallel to a top surface of the second insulating portion, and a via portion protruding from the interconnection portion toward the first surface. A width of the via portion decreases as a height in a direction from the second surface toward the first surface increases. The active surface of the first semiconductor chip is adjacent to the second surface.

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

Semiconductor package including outer conductive plate

A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.

A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.

A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.

Growing community of inventors

Hwaseong-si, South Korea

Seokhyun Lee