Samsung Electronics Co., Ltd.

Seohee Park

Kong-Soo Lee

Teawon Kim

Yong Suk Tak

Yurim Kim

MinKyung Kang

Yongsuk Tak

Provided is a method of manufacturing a semiconductor device, the method including: forming a mold structure comprising insulation layers and sacrificial layers alternately and repeatedly stacked on a substrate; forming a channel hole extending through the mold structure; forming a blocking layer in the channel hole; forming a charge storage layer on the blocking layer; forming a tunnel insulation layer including a doping element on the charge storage layer; performing heat treatment to diffuse the doping element from the tunnel insulation layer to the charge storage layer; and forming a channel layer on the tunnel insulation layer.

Method of manufacturing semiconductor device comprising doping element in the charge storage layer

A semiconductor device includes a channel layer disposed on a substrate and a gate structure formed on or under the channel layer. The channel layer includes a single-layer oxide semiconductor material, the channel layer includes indium (In), gallium (Ga), and oxygen (O), the channel layer includes a first region, a second region, and a third region, the third region contacting the gate structure, a second region between the first region and the third region, the first region is the closer to the substrate than the second region and the third region, each of the first region and the third region has a concentration of Ga higher than a concentration of In, and the second region has a concentration of In higher than a concentration of Ga.

Semiconductor device

A semiconductor device includes: a substrate; a conductive line extending on the substrate in a first horizontal direction; an isolation insulating layer extending on the substrate and the conductive line in a second horizontal direction intersecting with the first horizontal direction, and defining a channel trench extending through the isolation insulating layer from an upper surface of the isolation insulating layer to a lower surface of the isolation insulating layer; a crystalline oxide semiconductor layer extending along at least a portion of an inner side surface of the channel trench and at least a portion of a bottom surface of the channel trench and coming in contact with the conductive line; and a gate electrode extending on the crystalline oxide semiconductor layer inside the channel trench in the second horizontal direction.

Growing community of inventors

Daejeon, South Korea

Seohee Park