Lsi Logic Corporation

Seng Sooi Lim

Chok J Chia

Wee Keong Liew

Patrick J Variot

Kumar Nagarajan

Maniam B Alagaratnam

A mold for use in encapsulating an integrated circuit, wherein an encapsulant is injected into the mold during packaging of the integrated circuit. The improvement to the mold is a shaped member having an abutting surface for contacting a surface of the integrated circuit and thereby substantially preventing encapsulant from adhering to the surface of the integrated circuit, whereby the surface of the integrated circuit is left exposed. Because the surface of the integrated circuit is left exposed, the encapsulant used to encapsulate the integrated circuit does not form a thermal barrier between the integrated circuit and the exterior of the package. Thus, the packaged integrated circuit is able to more efficiently conduct heat away from the integrated circuit.

Molded integrated circuit package

An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound. Fluid communication between the plurality of vias and the air space may be provided by not tenting the vias with a solder mask layer, or by removing any solder mask or other material which may have filled or tented over the vias during processing of the substrate.

Overmold integrated circuit package

A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.

Mechanically interlocking ball grid array packages and method of making

A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant. The liquid encapsulant is preferably a C4 underfill material. By injecting the liquid encapsulant under pressure, the amount of time required to dispense the liquid encapsulant is reduced as well as the number of voids present in the liquid encapsulant. Following at least partial curing of the encapsulant, the mold sections are separated, and the packaged semiconductor device is removed. When fully cured and hardened, the encapsulant adheres to the adjacent surfaces of the integrated circuit and the substrate, essentially interlocking the surfaces.

System and method for packaging an integrated circuit using encapsulant

A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating. Electroplating the exposed trace areas on the IC substrate with conductive material (such as gold or nickel) by using the removable plating bus as the electrical connection to the exposed metal traces and removing the removable plating bus after electroplating is finished.

Growing community of inventors

San Jose, CA, United States of America

Seng Sooi Lim