Taiwan Semiconductor Manufacturing Comp. Ltd.

Sen-Shan Yang

Chen-Ming Huang

Pang-Yen Tsai

Ying-Chen Chao

Tien-Chen Hu

Keng-Hui Liao

Wei-Cheng Ku

Wi William Lee

A method for reducing stress migration in the copper interconnect line is set forth. In accordance with the method, two anneal steps take place: The first step is at low temperature and of relatively short duration (e.g., about 25-300&#xb0; C., and about 10 seconds-10 hours). After the first anneal, the wafer is cooled to room temperature. The second step is performed after the cooling step; a higher anneal temperature and longer time duration is needed to enhance performance.

Method of reducing stress migration in integrated circuits

Local electrochemical deplating of alignment mark regions of semiconductor wafers is disclosed. A tank holds an electrolytic solution. A primary cathode submersed within the solution is at least partially insulated therefrom. An electrochemically metal plated semiconductor wafer submersed within the solution acts as an anode, and has alignment mark regions. Extension cathodes submersed within the electrolytic solution are each at least partially insulated, except for a part of a first end and a second end thereof. The first end part is closely positioned over a corresponding alignment mark region, whereas the second end is situated on a corresponding exposed part of the primary cathode. A power source has its positive terminal operatively coupled to the primary cathode and its negative terminal operatively coupled to the wafer. Current from the power source electrochemically deplates the metal substantially from the alignment mark regions, substantially exposing the alignment marks within these regions.

Local electrochemical deplating of alignment mark regions of semiconductor wafers

A method and an apparatus for removing coating layers from the top of alignment marks on a wafer situated in a spin processor are described. The method may be carried out by first providing a spin process equipped with a rotatable wafer pedestal, then providing a wafer that has at least one alignment mark covered by a coating layer, mounting an edge ring on an outer periphery of the wafer pedestal, the edge ring has at least one tab section extending outwardly from an inner periphery of the edge ring, then positioning the wafer faced down and supported by an inert gas flow on the edge ring such that a narrow gap is formed between the tab section on the edge ring and the alignment marks and dispensing an etchant onto a backside of the wafer while rotating.

Method and apparatus for removing coating layers from alignment marks on a wafer

An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350&deg; C. in an inert gas in about 2 min., and then cooled down to not higher than 70&deg; C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.

Growing community of inventors

Tainan, Taiwan

Sen-Shan Yang