National Semiconductor Corporation

Sek Hoi Chong

Peng Soon Lim

Shee Min Yeong

You Chye How

Terh Kuen Yii

Chin Chai Gan

Tze Kang Tang

Hai Ching Tan

Danny Cher Hau Koh

Fuen Siang Ng

Eugene Kai Poh Wong

Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Methods and systems of packaging integrated circuits

Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package.

Panel level methods and systems for packaging integrated circuits with integrated heat sinks

An improved leadframe panel suitable for use in packaging IC dice for use in power applications is described. The described leadframe panel enables more efficient means of encapsulation and singulation as compared with a conventional power leadframe panel. Additionally, a thin IC power package is described that enables increased package heat dissipation, the use of a larger die attach pad as well as the use of a larger die as compared with conventional power devices.

Leadframe panel for power packages

Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed.

Optical leadless leadframe package

The voltage at a node of an integrated circuit can be measured or controlled using a two-wire kelvin contact with spring-based probe pins by offsetting and tapering the lower end section of the spring-based probe pin. As a result, multiple spring-based probe pins can be connected to a single contact bump, such as a solder bump.

Spring-based probe pin that allows kelvin testing

An apparatus for electrical testing of semiconductor devices is provided. A printed circuit board is provided. A first plurality of probe pins for probing bump connectors is electrically and mechanically connected to the printed circuit board. A second plurality of probe pins for probing probe pads is electrically and mechanically connected to the printed circuit board.

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Melaka, Malaysia

Sek Hoi Chong