Intel Corporation

Sony Group Corporation

Google Inc.

Sony Corporation

Tahoe Research, Ltd.

Seiyon Kim

Kelin J Kuhn

Rafael Rios

Stephen M Cea

Willy Rachmady

Anand S Murthy

Tahir Ghani

Annalisa Cappellani

Jack T Kavalieros

Ian A Young

Glenn A Glass

Martin D Giles

Mark Armstrong

Uygar E Avci

Abhijit Jayant Pethe

Cory E Weber

Rishabh Mehandru

Peter Chang

Daniel Henry Morris

Titash Rakshit

Daniel Bourne Aubertine

Seung Hoon Sung

Karthik Jambunathan

Patrick H Keys

Matthew V Metz

Van H Le

Patrick R Morrow

Ranjith Kumar

Joshua M Howard

Sasikanth Manipatruni

Kevin Lai Lin

Sanaz Kabehie Gardner

Chandra S Mohapatra

Ashish Agrawal

Daniel A Simon

Michael G Haverty

Chytra Pawashe

Sadasivan Shankar

Fahmida Ferdousi

Gilbert W Dewey

Benjamin Chu-Kung

Aaron D Lilak

Yih Wang

Ruth Amy Brain

Nadia M Rahhal-Orabi

Gopinath Bhimarasetti

Jun Sung Kang

Raseong Kim

Anurag Chaudhry

Harry Gomez

Chul-Hyun Lim

Mayank Sahni

Dmitri E Nikonov

Szuya S Liao

Peter L D Chang

Ashish Verma Penumatcha

Ibrahim Ban

James M Powers

Sou-Chi Chang

Curtis W Ward

Daniel Pantuso

Marc C French

Lei Jiang

Patrick Theofanis

Sherry R Taft

Jorge A Munoz

Edwin B Ramayya

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Integration methods to fabricate internal spacers for nanowire devices

Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Silicon and silicon germanium nanowire structures

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Nanowire structures having non-discrete source and drain regions

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

Nanowire transistor fabrication with hardmask layers

Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

Multilayer insulator stack for ferroelectric transistor and capacitor

Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Nanowire structures having wrap-around contacts

Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

Field effect transistors having ferroelectric or antiferroelectric gate dielectric structure

Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

Replacement metal COB integration process for embedded DRAM

An integrated circuit structure comprises a substrate. An antiferroelectric gate oxide is above the substrate, the antiferroelectric gate oxide comprising a perovskite material. A gate electrode is over at least a portion of the gate oxide.

Antiferroelectric perovskite gate oxide for transistor applications

Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a 'FE capacitor'). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

Memory cell with a ferroelectric capacitor integrated with a transtor gate

Growing community of inventors

Portland, OR, United States of America

Seiyon Kim