Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Seiro Miyoshi

Eishi Shiobara

Yoshihiro Yanai

Toshiya Kotani

Yoshihiko Nakano

Yasunobu Onishi

Chikaaki Kodama

Kentaro Matsunaga

Shuji Hayase

Hiromitsu Mashita

Masaki Narita

Fumiharu Nakajima

Yasuhiko Sato

Takeshi Koshiba

Hideto Matsuyama

Hidefumi Mukai

Rikako Kani

Sawako Yoshikawa

Tetsuaki Matsunawa

Takuro Urayama

Taiki Kimura

Shinichi Ito

Hiroyuki Yano

Yukiteru Matsui

Toshiro Hiraoka

Toru Ushirogouchi

Hirokazu Kato

Daisuke Kawamura

Koichi Matsuno

Yoshikuni Tateyama

Takeshi Nishioka

Kazunori Iida

Toshiyuki Aritake

Maki Miyazaki

Masako Kinoshita

According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.

Manufacturing method for a semiconductor device, pattern generating method and nontransitory computer readable medium storing a pattern generating program

According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.

Pattern data generation method, pattern verification method, and optical image calculation method

According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result.

Defect pattern evaluation method, defect pattern evaluation apparatus, and recording media

According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.

Pattern forming method and method of manufacturing semiconductor device

According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.

Pattern forming method

According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.

Acceptance determining method of blank for EUV mask and manufacturing method of EUV mask

In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.

Pattern forming method, manufacturing method of semiconductor device, and template manufacturing method

A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure.

Method of manufacturing semiconductor device

A method for treating a substrate before exposing the substrate to which a resist is applied, includes, rinsing the substrate to which a resist is applied, and holding the rinsed substrate in an atmosphere. The atmosphere substantially contains no moisture until conveying the substrate to an exposure apparatus.

Method for treating substrate, method for conveying substrate, and apparatus for conveying substrate

A substrate-processing apparatus includes a sample table which mounts thereon a to-be-processed substrate, a first line which supplies a chemical solution, a second line which supplies a cleaning liquid, a three-way valve connected to the first and second lines and configured to select one of the first and second lines, a filter provided across the first line upstream of the three-way valve, and configured to eliminate a foreign material from the chemical solution, and a nozzle provided downstream of the three-way valve and configured to discharge the chemical solution or the cleaning liquid when the first or second line is selected via the three-way valve. The three-way valve selects the first line when the substrate is coated with the chemical solution, and selects the second line in other cases.

Substrate processing apparatus and method

A method of forming a pattern which comprises the steps of, forming an organosilicon film on a work film, the organosilicon film comprising an organosilicon compound having a silicon-silicon bond in a backbone chain thereof and a glass transition temperature of 0&deg; C. or more, forming a resist pattern on the organosilicon film, and transcribing the resist pattern on the organosilicon film through an etching of the organosilicon film by making use of an etching gas containing at least one kind of atom selected from the group consisting of chlorine, bromine and iodine. The organosilicon pattern obtained by the etching is employed as a mask for patterning the work film.

Method of forming pattern

A polysilane having a repeating unit represented by the following general formula (LPS-I), ##STR1## wherein A is a bivalent organic group, R.sup.1 substituents may be the same or different and are selected from hydrogen atom and substituted or unsubstituted hydrocarbon group and silyl group. The polysilane is excellent in solublity in an organic solvent so that it can be formed into a film by way of a coating method, which is excellent in mechanical strength and heat resistance. The polysilane can be employed as an etching mask to be disposed under a resist in a manufacturing method of a semiconductor device. The polysilane exhibits anti-reflective effect during exposure, a large etch rate ratio in relative to a resist, and excellent dry etching resistance.

Method of forming a pattern using polysilane

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Mie, Japan

Seiro Miyoshi