Nec Corporation

Tokyo Electron Limited

Electron Tohoku Limited

Seiichi Shishiguchi

Tatsuya Suzuki

Masao Mikami

Hideo Kawano

Akira Mineji

Tomoko Yasunaga

Keiji Shiotani

Hiroaki Kikuchi

Yoshihiro Takaishi

Hiroshi Kitajima

Masato Sakao

Takeshi Akimoto

Shuichi Saito

Shizuo Oguro

Kousuke Miyoshi

Shuichi Ohya

Tohru Aoyama

Fumitoshi Toyokawa

Kazuhide Hasebe

Kiyonori Kajiyana

Nobuaki Shigematsu

A fabrication method of a semiconductor device is provided, which makes it possible to form shallow extensions (e.g., 0.1 &mgr;m or less in depth) of source/drain regions of a MOSFET with a double drain structure. In the step (a), a gate electrode is formed over a main surface of a single-crystal Si substrate of a first conductivity type through a gate insulating film. In the step (b), a dopant of a second conductivity type is ion-implanted into the substrate at an acceleration energy of 1 keV or lower under a condition that the amount of point defects induced in this step (b) is minimized or decreased, thereby forming first and second doped regions of the second conductivity type. In the step (c), a pair of sidewalls spacers are formed. In the step (d), a dopant of the second conductivity type is ion-implanted into the substrate, thereby forming third and fourth doped regions of the second conductivity type having a depth greater than the first and second doped regions and a lower dopant concentration than the first and second doped regions to be overlapped therewith. In the step (e), the substrate is subjected to an annealing process, thereby constituting one of a pair of source/drain regions with a double drain structure by the first and third doped regions and the other thereof by the second and fourth doped regions.

Fabrication method of semiconductor device using ion implantation

A method of manufacturing a semiconductor device has a step whereby, when forming a gate oxide film, a thin oxide film is left on a silicon substrate onto which it is formed and whereby a heavy metal at the surface of the silicon substrate is diffused into the substrate, and a step of forming a gate oxide film onto the silicon substrate.

Removal of metal contaminants from the surface of a silicon substrate by diffusion into the bulk

A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching. If unwanted grains of poly-Si or amorphous Si are grown on the first and second dielectric sidewalls in the selective epitaxial growth process, the unwanted grains are oxidized and removed, thereby preventing electrical short-circuit from occurring between the gate electrode and the first and second source/drain regions through the unwanted grains deposited on the first and second dielectric sidewalls.

Fabrication method of semiconductor device using selective epitaxial growth

The present invention provides a method of forming gate side wall insulation films on side walls of a gate electrode on a gate insulation film over a silicon substrate surface. The method comprises The following steps. Gate side wall insulation films are selectively formed on side walls of a gate electrode. A silicon film is selectively grown on at least any one of a top of the gate electrode and on the silicon substrate surface. Surface regions of the gate side wall insulation films are etched.

Method of forming a MOS field effect transistor with improved gate side

A method for manufacturing a semiconductor device comprises the steps of forming consecutively a silicon oxide layer and a test epitaxial layer in a test pattern area on a silicon wafer, forming an epitaxial layer in a product area for semiconductor devices and on the test epitaxial layer simultaneously, measuring a total thickness of the epitaxial layer and the test epitaxial layer formed in the test pattern area by infrared interference, and determining the thickness of the epitaxial layer formed in the product area based on the total thickness to control the thickness of the epitaxial layer in the product area. A thickness control for a very thin epitaxial layer can be obtained.

Method for manufacturing a semiconductor device

Disclosed is a method for selectively forming silicon layers on diffusion layers of a MOS transistor so as to form an elevated structure in order to lower a resistance of the source/drain region. The method is aimed to lower the temperature required for the process of forming the elevated structure. In order to accomplish the foregoing object, the method of manufacturing a semiconductor device according to the invention is characterized in that titanium silicide layers are laminated in two steps. First, thin titanium films are grown on the diffusion layers and thereafter an annealing is applied to form titanium silicide layers; and then the titanium films remaining unreacted on the insulating films are removed. Thereafter, another silicon layer is selectively grown on the titanium silicide layers, followed by a new titanium layer. A second annealing step is performed to obtain a second titanium silicide layer laminated on the first titanium suicide layer. The titanium layers and the titanium silicide layers act as gettering films for oxygen from native oxide films formed on the surface.

Method for manufacturing a semiconductor device having a refractory

A vapor-phase growth system able to avoid fluctuation of the heating performance of a heater during repeated growth processes is provided. This system includes a reactor, a substrate holder for holding a substrate, and a heater for heating the substrate held by the holder. The holder and the heater are placed in an inner space of the reactor. The holder and the substrate held by the holder divide an inner space of the reactor to thereby form a growth chamber in which a thin film is grown during a growth process and a heater chamber in which the heater is placed. The holder has a supporting member on which the substrate is placed. At least a part of the member is made of the same material as that of the thin film. The supporting member is made of a SOI substrate.

Cold-wall operated vapor-phase growth system

A silicon semiconductor substrate including a silicon semiconductor layer at one of upper and lower surfaces thereof, the silicon semiconductor layer being composed of polysilicon or noncrystal silicon and containing oxygen in the range of 2 atomic % to 20 atomic % both inclusive, nitrogen in the range of 4 atomic % to 20 atomic % both inclusive, or both nitrogen at 2 atomic % or greater and oxygen at 1 atomic % or greater. The polysilicon or noncrystal silicon semiconductor layer acts as a core for extrinsic gettering. In the silicon semiconductor substrate, the gettering performance is not deteriorated, even if the silicon semiconductor substrate experiences thermal treatment. Thus, it is possible to get rid of contamination caused by heavy metals in the silicon semiconductor substrate.

Silicon semiconductor substrate and method of fabricating the same

In a method for forming a capacitor, after preparing a substrate having at least one device area thereon, an amorphous silicon film containing one type of dopant is formed on the device area. A mask layer comprising mask islands is formed and distributed on a surface of the amorphous silicon film. The surface of the amorphous silicon is dry-etched by using the mask layer as a selective etching mask to produce a jagged surface having a lot of protrusions. After forming the jagged surface, the amorphous silicon film is changed into a polycrystalline silicon film serving as a storage electrode. Finally, a dielectric film and then another storage electrode are formed sequentially on the jagged surface of the storage electrode.

Method for forming capacitor electrode having jagged surface

On treating a substrate surface of a single crystal silicon substrate, Ge ions are preliminarily implanted into the substrate surface to be formed as a Ge-implanted silicon film on the single crystal silicon substrate. A film surface of Ge-implanted silicon film is treated by oxidizing the film surface to form a spontaneous oxide film. Subsequently, the spontaneous oxide film is subjected to a heat treatment in a reduced-pressure atmosphere to remove the spontaneous oxide film. Alternatively, the spontaneous oxide film is subjected to a heat treatment with a reducing gas of, for example, a hydrogen gas, a silane-based gas, or a GeH.sub.4 gas supplied onto the spontaneous oxide film to remove the spontaneous oxide film. Preferably, the Ge ions are preliminarily implanted into the substrate surface to be formed as Ge-implanted silicon film which consists, in atomic percent, essentially of at least 1% Ge.

Substrate surface treatment method capable of removing a spontaneous

Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capacitor having a capacitor electrode connected to the source region through a contact hole provided in the first and second insulating film.

Semiconductor memory device having trench isolation regions and bit

A number of wafers are loaded into a reaction vessel on a wafer boat; monosilane gas, phosphine gas and N.sub.2 O gas are supplied to form amorphous silicon film doped with, e.g., phosphorus; and then the wafers are annealed in, e.g., a different reaction tube to polycrystallize the amorphous silicon film. Os (Oxygen) generated by decomposition of N.sub.2 O are taken into the film. The Os become nuclei of the silicon crystals, and the crystals become fine and have size uniformity. As a result, high uniformity of resistance values of micronized devices of the polysilicon film can be obtained. Resistance values of the polysilicon film can be easily controlled by addition of oxygen. As a result, high uniformity of resistance values of micronized devices of the polysilicon film can be obtained.

Method for forming doped polysilicon films

A method of forming a silicon-based thin film for burying contact holes having a high aspect ratio is disclosed. The method comprises the steps of forming contact holes in an insulating film provided on a semiconductor substrate, and growing a silicon-based (silicon or silicon alloys) film containing impurities by Chemical Vapor Deposition to bury the contact holes. The growth is performed by simultaneously feeding a material gas for forming the silicon-based film and an etching gas for etching the silicon-based film, where the material gas is fed under surface reaction limiting conditions to equalize gas concentrations inside and outside said contact holes, and the etching gas is fed under supply rate limiting conditions to make the gas concentration outside the contact hole higher than that at the bottom of the contact hole.

Method for producing silicon film to bury contact hole

First, a metal layer is deposited on a silicon film surface to form a silicide layer in an interface between the silicon film and the metal layer. Subsequently, the metal layer is all removed by etching such that silicide islands are left on the surface of the silicon film, and then the exposed silicon film surface is dry-etched by using the silicide islands as a selective mask.

Method of forming silicon film having jagged surface

The method of fabricating a poly-silicon resistor includes a step for providing a dopant gas and a nitrous oxide gas as well as a silane gas to thereby deposit a silicon layer on a substrate by chemical vapor deposition under a deposition temperature not higher than 600 degrees centigrade so that the silicon layer includes the dopant of the dopant gas and oxygen, and a step for annealing the silicon layer under a temperature not lower than 600 degrees centigrade.

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Tokyo, Japan

Seiichi Shishiguchi