Kabushiki Kaisha Toshiba

Asahi Kogaku Kogyo Kabushiki Kaisha

International Business Machines Corporation

Asahi Kogaku Kogyo K.k.

Seiichi Mori

Yuji Takeuchi

Michiharu Matsui

Riichiro Shirota

Takeshi Kamigaichi

Masayuki Ichige

Mitsuhiro Noguchi

Shigeru Atsumi

Hiroaki Hazama

Koji Sakui

Koji Hashimoto

Masataka Takebuchi

Kuniyoshi Yoshikawa

Masahisa Sonoda

Tatsuaki Kuji

Atsuhiro Sato

Hironori Banba

Masao Kuriyama

Hiroaki Tsunoda

Masatoshi Takano

Nobuaki Otsuka

Toshiharu Watanabe

Hirohisa Iizuka

Seiji Yamada

Kazuhiro Ichinokawa

Yukio Nishiyama

Naruhiko Kaji

Kazuaki Isobe

Hirotaka Ogihara

Yoshiko Araki

Masao Tanimoto

Tooru Tanzawa

Toru Tanzawa

Masaki Sato

Hideo Kato

Junichi Miyamoto

Tadashi Iguchi

Susumu Shuto

Junji Shirakawa

Hidetoshi Saito

Takeshi Matsushita

Toshimasa Yamanaka

Keisuke Yonehama

Kazuhito Narita

Nobuaki Ohtsuka

Masato Matsubara

Masayuki Ainoya

Eiji Sakagami

Masakazu Hirano

Yoshiharu Hirata

Satoshi Hokamura

Katsuhiro Ishida

Toshiaki Idaka

Yoichi Ohshima

Hiroyuki Sasaki

Satoru Morisawa

Norio Ootani

Kenichi Sasaki

Miwa Tanaka

Takeyuki Ishihara

Tesuo Kanno

Takahiro Kikuchi

Shogo Nobumori

Takeshi Shinagawa

Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Nonvolatile semiconductor memory device having element isolating region of trench type

A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.

Semiconductor memory preventing an electric short circuit between a word line and a semiconductor substrate, and manufacturing method for the semiconductor memory

A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film () in the cell array region, gate oxide film () for a high-voltage circuit and gate oxide film () for a low-voltage circuit both in the peripheral circuit to respectively optimum values of thickness, and covering them with a first-layer polycrystalline silicon film (). After that, device isolation grooves () are formed and buried with a device isolation insulating film (). The first-layer polycrystalline silicon film () is a non-doped film, and after device isolation, a second-layer polycrystalline silicon film () is doped with phosphorus in the cell array region to form floating gates made of the first-layer polycrystalline silicon film () and the second-layer polycrystalline silicon film (). In the peripheral circuit, gate electrodes are made of a multi-layered film including the first-layer polycrystalline silicon, film (), second-layer polycrystalline silicon film () and third-layer polycrystalline silicon film, and impurities are ion implanted thereafter to respective transistor regions under respectively optimum conditions.

Semiconductor memory integrated circuit and its manufacturing method

A semiconductor device includes an element isolation insulating film adjacent to an active area, a gate insulating film formed on a semiconductor substrate in the active area, paired gate electrodes located on the gate insulating film, a contact plug located on the active area between the gate electrodes, a pair of first upper lines located on the gate electrodes, a second upper line located on the gate electrodes, and a stopper film above upper surfaces of the gate electrodes and side surfaces of the gate electrodes. The element isolation insulating film has a first height of an upper surface thereof with reference to an upper surface of the semiconductor substrate and a second height of another upper surface thereof with reference to another upper surface of the semiconductor substrate. The first height is smaller than the second height.

Semiconductor device and method of manufacturing the same

A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

Nonvolatile semiconductor memory

A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 10/cmor less. The inter-insulating layer also may includes a silicon oxide layer serving as a layer contiguous to at least one of the floating gate and the control gate, and having a lower trap density than that of a silicon nitride layer formed by a CVD method.

Non-volatile semiconductor memory device

A first insulation film, a first conductor film, and a cap are sequentially formed on a semiconductor substrate. The first insulation film, the first conductor film, and the cap, and the substrate are etched in the same pattern. A second insulation film is placed in that etched pattern. The cap is removed. A second conductor film is formed on the side face of the second insulation film.

Semiconductor device having two-layered charge storage electrode

A semiconductor device is disclosed, which comprises trench type device isolation regions formed in a semiconductor substrate, semiconductor active regions electrically isolated by the isolation regions, a first electrode layer formed to self-align to the isolation regions, and a second electrode layer formed over the first electrode layer with an insulating film interposed therebetween, the top of each of the isolation regions being located, in an area where the second electrode layer is present, at a first level below the top of the first electrode layer and above the surface of the active regions and, in an area where the second electrode layer is not present, at a second level below the first level, and the surface of the active regions being at substantially the same level in the area where the second electrode layer is present and in the area where the second electrode layer is not present.

Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.

Manufacturing method of semiconductor device with filling insulating film into trench

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Tokyo, Japan

Seiichi Mori