Sandia Corporation

National Technology & Engineering Solutions of Sandia, LLC

Seethambal S Mani

Jeffry Joseph Sniegowski

Randolph R Kay

James G Fleming

Paul J Resnick

Darwin K Serkland

Peggy J Clews

Douglas Chandler Trotter

Scott D Habermehl

Dale L Hetherington

James E Stevens

Adam Jones

Thomas M Gurrieri

Dahwey Chu

Thomas W Krygowski

David V Campbell

Andrew Lea Starbuck

Robert S Blewer

Subhash L Shinde

Andrew Pomerene

Michael L Holmes

Joy M Barker

Reinhard Brock

Jeffrey L Rienstra

Steven R Volk

A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.

Method of fabricating photosensitive devices with reduced process-temperature budget

A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.

Focal plane array with modular pixel array components for scalability

An etching composition and method is disclosed for removing an oxide sacrificial material during manufacture of semiconductor devices including micromechanical, microelectromechanical or microfluidic devices. The etching composition and method are based on the combination of hydrofluoric acid (HF) and sulfuric acid (HSO). These acids can be used in the ratio of 1:3 to 3:1 HF:HSOto remove all or part of the oxide sacrificial material while providing a high etch selectivity for non-oxide materials including polysilicon, silicon nitride and metals comprising aluminum. Both the HF and HSOcan be provided as 'semiconductor grade' acids in concentrations of generally 40-50% by weight HF, and at least 90% by weight HSO.

Selective etchant for oxide sacrificial material in semiconductor device fabrication

A process is disclosed for forming a microelectromechanical (MEM) structure on a substrate having from 5 to 6 or more layers of deposited and patterned polysilicon. The process is based on determining a radius of curvature of the substrate which is bowed due to accumulated stress in the layers of polysilicon and a sacrificial material used to buildup the MEM structure, and then providing one or more stress-compensation layers on a backside of the substrate to flatten the substrate and allow further processing.

Process for fabricating a microelectromechanical structure

A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 &deg; C. in the presence of gaseous nitrogen trifluoride (NF,). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF,) at an elevated temperature, preferably about 450&deg; C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact. The present invention can be applied to many different types of MEM devices including microrelays, micromirrors and microengines. Additionally, the tungsten wear-resistant coating of the present invention can be used to enhance the hardness, wear resistance, electrical conductivity, optical reflectivity and chemical inertness of one or more semiconductor surfaces within a MEM device.

Tungsten coating for improved wear resistance and reliability of microelectromechanical devices

Growing community of inventors

Albuquerque, NM, United States of America

Seethambal S Mani