International Business Machines Corporation

Zeon Corporation

Globalfoundries Inc.

Tokyo Electron Limited

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Sebastian Ulrich Engelmann

Masahiro Nakamura

Nicholas C M Fuller

Eric Andrew Joseph

Hiroyuki Miyazoe

Robert L Bruce

Michael A Guillorn

Ying Di Zhang

Nathan P Marchack

Markus Brink

Guy M Cohen

Josephine B Chang

Richard Stephan Wise

Sarunya Bangsaruntip

Mahmoud M Khojasteh

Ravi K Dasaka

Jeffrey W Sleight

Kevin K Chan

Cyril Cabral, Jr

Yu Zhu

Hsinyu Tsai

Hongwen Yan

Benjamin L Fletcher

George Gabriel Totir

Qingyun Yang

Steve Donald Holmes

Michael S Gordon

Leland Chang

Eugene John O'Sullivan

Deborah A Neumayer

Stephen Mark Rossnagel

Lidija Sekaric

Satyavolu S Papa Rao

Adam M Pyzyna

John M Papalia

Ashish V Jagtiani

Jyotica V Patel

Masahiro Yamazaki

Bang N To

Christopher Scerbo

Isaac Lauer

Qinghuang Lin

Jeng-Bang Yau

Anthony J Annunziata

Renee Tong Mo

Satyanarayana Venkata Nitta

Dario Leonardo Goldfarb

John Christopher Arnold

Li-Wen Hung

Gen Pei Lauer

Martin Glodde

Jeffrey C Shearer

Lynne Marie Gignac

Cornelia Tsang Yang

Marinus Hopstaken

Nicholas Joy

James Vichiconti

Takefumi Suzuki

Ryan M Martin

Marinus Johannes Petrus Hopstaken

Devi Koty

Thitima Suwannasiri

Jeff Waksman

Luxherta Buzi

A process of improving a profile and repairing sidewall damage for phase change memory devices. The process includes applying inert ion beam etching to trim a sidewall of a layer of phase change memory material in a phase change memory device, where the sidewall has been damaged in reactive ion etching using halogens. In the process, the inert ion beam etching is with low energy. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined low temperature. In the process, applying the inert ion beam etching to trim the sidewall is at a predetermined small angle between an inert ion beam and a surface tangent of the sidewall.

Applying inert ion beam etching for improving a profile and repairing sidewall damage for phase change memory devices

A method of plasma processing that includes maintaining a plasma processing chamber between 10° C. to 200° C., flowing oxygen and nitrogen into the plasma processing chamber, where a ratio of a flow rate of the nitrogen to a flow rate of oxygen is between about 1:5 and about 1:1, and etching a ruthenium/osmium layer by sustaining a plasma in the plasma processing chamber.

Methods for etching metal films using plasma processing

A method for etching a poly-granular metal-based film includes providing a flow of a background gas in a plasma etching chamber containing a semiconductor structure including the poly-granular metal-based film formed over a substrate with a mask patterned over the poly-granular metal-based film. The method also includes applying a source power to generate a background plasma from the background gas, and providing a flow of a modifying gas while maintaining the flow of the background gas to generate a modifying plasma that produces a surface modification region with a substantially uniform depth in the top surface of the poly-granular metal-based film exposed by the mask. The method further includes stopping the flow of the modifying gas while maintaining the flow of the background gas, and applying a biasing power to the substrate to remove the surface modification region.

Layer-by-layer etching of poly-granular metal-based materials for semiconductor structures

A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to the gate structure and plasma cleaning the III-V material on the side regions adjacent to the gate structure. The III-V material is plasma doped on the side regions adjacent to the gate structure to form plasma doped extension regions that partially extend below the gate structure.

III-V extension by high temperature plasma doping

Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.

Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch

A silicon nitride cap on a gate stack is removed by etching with a fluorohydrocarbon-containing plasma subsequent to formation of source/drain regions without causing unacceptable damage to the gate stack or source/drain regions. A fluorohydrocarbon-containing polymer protection layer is selectively deposited on the regions that are not to be etched during the removal of the nitride cap. The ability to remove the silicon nitride material using gas chemistry, causing formation of a volatile etch product and protection layer, enables reduction of the ion energy to the etching threshold.

High selectivity nitride removal process based on selective polymer deposition

A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.

Method of integrated circuit (IC) chip fabrication

After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

Self-aligned trench metal-alloying for III-V nFETs

Fabrication of a semiconductor device includes providing a semiconductor substrate, and a dielectric layer disposed over the semiconductor substrate. The dielectric layer includes a plurality of vias extending through the dielectric layer to the top surface of the semiconductor substrate. Each of the vias contains an organic planarization material. The dielectric layer is removed by plasma etching with a gas having a general chemical formula of CHFwherein x is greater than 3 and y is greater than z to provide an array of pillars including the organic planarization material on the semiconductor substrate.

Image reversal process for tight pitch pillar arrays

A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.

Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits

A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.

Plasma shallow doping and wet removal of depth control cap

After bonding a second substrate to a first substrate through a bonded material layer to provide a bonded structure, through dielectric via (TDV) openings of different depths are concurrently formed in the bonded structure by performing a single anisotropic etch using fluorine-deficient species that are obtained by dissociation of fluorocarbon-containing molecules.

Rapid oxide etch for manufacturing through dielectric via structures

A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH)(NO)),(CAN).

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White Plains, NY, United States of America

Sebastian Ulrich Engelmann